Applying power to a standard logic chip, SRAM, or EPROM, usually results in OUTPUT pinstracking the applied voltage as it rises. Programmable logic attempts to emulate that behavior,but physics forbids perfect emulation, due to the device programmability. It requires care tospecify the pin behavior, because programmable parts encounter unknown variables – yourdesign and your power environment.
上传时间： 2013-11-24
上传用户：253189838
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its OUTPUT clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO OUTPUT is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2014-11-26
上传用户：erkuizhang
This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/OUTPUT precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to be selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully synchronous interface through the ce, clk,and rst ports.
上传时间： 2013-12-14
上传用户：逗逗666
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single OUTPUT video stream. The OUTPUT of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
欢迎使用 PowerPCB 教程。本教程描述了 PADS-PowerPCB 的绝大部分功能和特点，以及使用的各个过程，这些功能包括： · 基本操作 · 建立元件(Component) · 建立板子边框线(Board outline) · 输入网表(Netlist) · 设置设计规则(Design Rule) · 元件(Part)的布局(Placement) · 手工和交互的布线 · SPECCTRA全自动布线器(Route Engine) · 覆铜(Copper Pour) · 建立分隔/混合平面层(Split/mixed Plane) · Microsoft的目标连接与嵌入(OLE)(Object Linking Embedding) · 可选择的装配选件(Assembly options) · 设计规则检查(Design Rule Check) · 反向标注(Back Annotation) · 绘图输出(Plot OUTPUT) 使用本教程后，你可以学到印制电路板设计和制造的许多基本知识。
上传时间： 2013-10-08
上传用户：x18010875091
针对嵌入式机器视觉系统向独立化、智能化发展的要求，介绍了一种嵌入式视觉系统--智能相机。基于对智能相机体系结构、组成模块和图像采集、传输和处理技术的分析，对国内外的几款智能相机进行比较。综合技术发展现状，提出基于FPGA+DSP模式的硬件平台，并提出智能相机的发展方向。分析结果表明，该系统设计可以实现脱离PC运行，完成图像获取与分析，并作出相应输出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding OUTPUT.
上传时间： 2013-11-14
上传用户：无聊来刷下
为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中，测试结果表明，调制电路能正确选相，解调电路输出数据与QDPSK调制输入数据完全一致，达到了预期的设计要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the OUTPUT data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上传时间： 2013-10-28
上传用户：jyycc
Hyperlynx仿真应用:阻抗匹配.下面以一个电路设计为例，简单介绍一下PCB仿真软件在设计中的使用。下面是一个DSP硬件电路部分元件位置关系(原理图和PCB使用PROTEL99SE设计)，其中DRAM作为DSP的扩展Memory(64位宽度，低8bit还经过3245接到FLASH和其它芯片)，DRAM时钟频率133M。因为频率较高，设计过程中我们需要考虑DRAM的数据、地址和控制线是否需加串阻。下面，我们以数据线D0仿真为例看是否需要加串阻。模型建立首先需要在元件公司网站下载各器件IBIS模型。然后打开Hyperlynx,新建LineSim File(线路仿真—主要用于PCB前仿真验证)新建好的线路仿真文件里可以看到一些虚线勾出的传输线、芯片脚、始端串阻和上下拉终端匹配电阻等。下面，我们开始导入主芯片DSP的数据线D0脚模型。左键点芯片管脚处的标志，出现未知管脚，然后再按下图的红线所示线路选取芯片IBIS模型中的对应管脚。 3http://bbs.elecfans.com/ 电子技术论坛 http://www.elecfans.com 电子发烧友点OK后退到“ASSIGN Models”界面。选管脚为“OUTPUT”类型。这样，一样管脚的配置就完成了。同样将DRAM的数据线对应管脚和3245的对应管脚IBIS模型加上(DSP输出，3245高阻，DRAM输入)。下面我们开始建立传输线模型。左键点DSP芯片脚相连的传输线，增添传输线，然后右键编辑属性。因为我们使用四层板，在表层走线，所以要选用“Microstrip”，然后点“Value”进行属性编辑。这里，我们要编辑一些PCB的属性，布线长度、宽度和层间距等，属性编辑界面如下：再将其它传输线也添加上。这就是没有加阻抗匹配的仿真模型(PCB最远直线间距1.4inch，对线长为1.7inch)。现在模型就建立好了。仿真及分析下面我们就要为各点加示波器探头了，按照下图红线所示路径为各测试点增加探头：为发现更多的信息，我们使用眼图观察。因为时钟是133M，数据单沿采样，数据翻转最高频率为66.7M，对应位宽为7.58ns。所以设置参数如下：之后按照芯片手册制作眼图模板。因为我们最关心的是接收端(DRAM)信号，所以模板也按照DRAM芯片HY57V283220手册的输入需求设计。芯片手册中要求输入高电平VIH高于2.0V，输入低电平VIL低于0.8V。DRAM芯片的一个NOTE里指出，芯片可以承受最高5.6V，最低-2.0V信号(不长于3ns)：按下边红线路径配置眼图模板：低8位数据线没有串阻可以满足设计要求，而其他的56位都是一对一，经过仿真没有串阻也能通过。于是数据线不加串阻可以满足设计要求，但有一点需注意，就是写数据时因为存在回冲，DRAM接收高电平在位中间会回冲到2V。因此会导致电平判决裕量较小，抗干扰能力差一些，如果调试过程中发现写RAM会出错，还需要改版加串阻。
上传时间： 2013-12-17
上传用户：debuchangshi
为了提高直接转矩控制（DTC）系统定子磁链估计精度，降低电流、电压测量的随机误差，提出了一种基于扩展卡尔曼滤波（EKF）实现异步电机转子位置和速度估计的方法。扩展卡尔曼滤波器是建立在基于旋转坐标系下由定子电流、电压、转子转速和其它电机参量所构成的电机模型上，将定子电流、定子磁链、转速和转子角位置作为状态变量，定子电压为输入变量，定子电流为输出变量，通过对磁链和转速的闭环控制提高定子磁链的估计精度，实现了异步电机的无速度传感器直接转矩控制策略，仿真结果验证了该方法的可行性,提高了直接转矩的控制性能。 Abstract: In order to improve the Direct Torque Control（DTC） system of stator flux estimation accuracy and reduce the current， voltage measurement of random error， a novel method to estimate the speed and rotor position of asynchronous motor based on extended Kalman filter was introduced. EKF was based on d-p axis motor and other motor parameters （state vector: stator current， stator flux linkage， rotor angular speed and position； input: stator voltage； OUTPUT: staror current). EKF was designed for stator flux and rotor speed estimation in close-loop control. It can improve the estimated accuracy of stator flux. It is possible to estimate the speed and rotor position and implement asynchronous motor drives without position and speed sensors. The simulation results show it is efficient and improves the control performance.
上传时间： 2015-01-02
上传用户：qingdou
微电脑型单相交流集合式电表（单相二线系统） 特点： 精确度0.25%满刻度±1位数 可同时量测与显示交流电压,電流,頻率,瓦特,(功率因數/視在功率) 交流電壓,電流,瓦特皆為真正有效值(TRMS) 交流電流,瓦特之小數點可任意設定 瓦特單位W或KW可任意設定 CT比可任意設定(1至999) 輸入與輸出絕緣耐压 2仟伏特/1分鐘( 突波測試強度4仟伏特(1.2x50us) 數位RS-485界面 (Optional) 主要规格： 精确度: 0.1% F.S.±1 digit (Frequency) 0.25% F.S.±1 digit(ACA,ACV,Watt,VA) 0.25% F.S. ±0.25o(Power Factor) (-.300~+.300) 输入负载: <0.2VA (Voltage) <0.2VA (Current) 最大过载能力: Current related input: 3 x rated continuous 10 x rated 30 sec. 25 x rated 3sec. 50 x rated 1sec. Voltage related input: maximum 2 x rated continuous 过载显示: "doFL" 显示值范围: 0~600.0V(Voltage) 0~999.9Hz(Frequency)(<20% for voltage input) 0~19999 digit adjustable(Current,Watt,VA) 取样时间: 2 cycles/sec. RS-485通讯位址: "01"-"FF" RS-485传输速度: 19200/9600/4800/2400 selective RS-485通信协议: Modbus RTU mode 温度系数: 100ppm/℃ (0-50℃) 显示幕: Red high efficiency LEDs high 10.16 mm(0.4") 参数设定方式: Touch switches 记忆型式: Non-volatile E²PROM memory 绝缘抗阻: >100Mohm with 500V DC 绝缘耐压能力: 2KVac/1 min. (input/OUTPUT/power) 1600 Vdc (input/OUTPUT) 突波测试: ANSI c37.90a/1974,DIN-IEC 255-4 impulse voltage 4KV(1.2x50us) 使用环境条件: 0-50℃(20 to 90% RH non-condensed) 存放环境条件: 0-70℃(20 to 90% RH non-condensed) CE认证: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上传时间： 2015-01-03
上传用户：几何公差
