The CAT9534 is an 8-bit parallel input/OUTPUT portexpander for I²C and SMBus compatible applications.These I/O expanders provide a simple solution inapplications where additional I/Os are needed: sensors,power switches, LEDs, pushbuttons, and fans.The CAT9534 consists of an input port register, anOUTPUT port register, a configuration register, a polarityinversion register and an I²C/SMBus-compatible serialinterface.
上传时间： 2013-11-09
上传用户：liulinshan2010
基于PIC单片机的脉冲电源:设计了一种金属凝固过程用脉冲电源。该电源采用PIC16F877作为主控芯片，实现对窄脉冲电流幅值的检测，以及时电流脉冲幅值根据模糊PID算法进行闲环控制。使用结果表明：该电源的输出脉冲波形良好，电流幅值稳定，满足合金材料凝固过程的工艺要求且运行稳定可靠。关键词：脉冲电源；PIC16F877单片机；模糊PID；闲环控制 Abstract：A kind of pulse power supply was designed which uses in the metal solidification process ．．I11is power supply used PIC16F877 to take the master control chip reali on to the narrow pulse electric current peak-to-peak value examination，carried on the closed-loop control to the electric current pulse peak-to-peak value basis fuzzy PID algorithm．The use result indicated ，this power supply OUTPUT se profile is good，and the electric current peak-to-p~k value is stable，It satisfies the alloy material solidification process the technological requirement and movement stable reliable，Key words：p se po wer supply；PIC16F877single-chip microcontroller；f r PID；closed-loop control
上传时间： 2013-10-27
上传用户：xcy122677
有两种方式可以让设备和应用程序之间联系：1. 通过为设备创建的一个符号链；2. 通过输出到一个接口WDM驱动程序建议使用输出到一个接口而不推荐使用创建符号链的方法。这个接口保证PDO的安全，也保证安全地创建一个惟一的、独立于语言的访问设备的方法。一个应用程序使用Win32APIs来调用设备。在某个Win32 APIs和设备对象的分发函数之间存在一个映射关系。获得对设备对象访问的第一步就是打开一个设备对象的句柄。 用符号链打开一个设备的句柄为了打开一个设备，应用程序需要使用CreateFile。如果该设备有一个符号链出口，应用程序可以用下面这个例子的形式打开句柄：hDevice = CreateFile("\\\\.\\OMNIPORT3", GENERIC_READ | GENERIC_WRITE,FILE_SHARE_READ, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL ,NULL);文件路径名的前缀“\\.\”告诉系统本调用希望打开一个设备。这个设备必须有一个符号链，以便应用程序能够打开它。有关细节查看有关Kdevice和CreateLink的内容。在上述调用中第一个参数中前缀后的部分就是这个符号链的名字。注意：CreatFile中的第一个参数不是Windows 98/2000中驱动程序(.sys文件)的路径。是到设备对象的符号链。如果使用DriverWizard产生驱动程序，它通常使用类KunitizedName来构成设备的符号链。这意味着符号链名有一个附加的数字，通常是0。例如：如果链接名称的主干是L“TestDevice”那么在CreateFile中的串就该是“\\\\.\\TestDevice0”。如果应用程序需要被覆盖的I/O，第六个参数(Flags)必须或上FILE_FLAG_OVERLAPPED。 使用一个输出接口打开句柄用这种方式打开一个句柄会稍微麻烦一些。DriverWorks库提供两个助手类来使获得对该接口的访问容易一些，这两个类是CDeviceInterface, 和 CdeviceInterfaceClass。CdeviceInterfaceClass类封装了一个设备信息集，该信息集包含了特殊类中的所有设备接口信息。应用程序能有用CdeviceInterfaceClass类的一个实例来获得一个或更多的CdeviceInterface类的实例。CdeviceInterface类是一个单一设备接口的抽象。它的成员函数DevicePath()返回一个路径名的指针，该指针可以在CreateFile中使用来打开设备。下面用一个小例子来显示这些类最基本的使用方法：extern GUID TestGuid;HANDLE OpenByInterface( GUID* pClassGuid, DWORD instance, PDWORD pError){ CDeviceInterfaceClass DevClass(pClassGuid, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; CDeviceInterface DevInterface(&DevClass, instance, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; cout << "The device path is " << DevInterface.DevicePath() << endl; HANDLE hDev; hDev = CreateFile( DevInterface.DevicePath(), GENERIC_READ | GENERIC_WRITE, FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL ); if (hDev == INVALID_HANDLE_VALUE) *pError = GetLastError(); return hDev;} 在设备中执行I/O操作一旦应用程序获得一个有效的设备句柄，它就能使用Win32 APIs来产生到设备对象的IRPs。下面的表显示了这种对应关系。Win32 API DRIVER_FUNCTION_xxxIRP_MJ_xxx KDevice subclass member function CreateFile CREATE Create ReadFile READ Read WriteFile WRITE Write DeviceIoControl DEVICE_CONTROL DeviceControl CloseHandle CLOSECLEANUP CloseCleanUp 需要解释一下设备类成员的Close和CleanUp：CreateFile使内核为设备创建一个新的文件对象。这使得多个句柄可以映射同一个文件对象。当这个文件对象的最后一个用户级句柄被撤销后，I/O管理器调用CleanUp。当没有任何用户级和核心级的对文件对象的访问的时候，I/O管理器调用Close。如果被打开的设备不支持指定的功能，则调用相应的Win32将引起错误（无效功能）。以前为Windows95编写的VxD的应用程序代码中可能会在打开设备的时候使用FILE_FLAG_DELETE_ON_CLOSE属性。在Windows NT/2000中，建议不要使用这个属性，因为它将导致没有特权的用户企图打开这个设备，这是不可能成功的。I/O管理器将ReadFile和WriteFile的buff参数转换成IRP域的方法依赖于设备对象的属性。当设备设置DO_DIRECT_IO标志，I/O管理器将buff锁住在存储器中，并且创建了一个存储在IRP中的MDL域。一个设备可以通过调用Kirp::Mdl来存取MDL。当设备设置DO_BUFFERED_IO标志，设备对象分别通过KIrp::BufferedReadDest或 KIrp::BufferedWriteSource为读或写操作获得buff地址。当设备不设置DO_BUFFERED_IO标志也不设置DO_DIRECT_IO，内核设置IRP 的UserBuffer域来对应ReadFile或WriteFile中的buff参数。然而，存储区并没有被锁住而且地址只对调用进程有效。驱动程序可以使用KIrp::UserBuffer来存取IRP域。对于DeviceIoControl调用，buffer参数的转换依赖于特殊的I/O控制代码，它不在设备对象的特性中。宏CTL_CODE（在winioctl.h中定义）用来构造控制代码。这个宏的其中一个参数指明缓冲方法是METHOD_BUFFERED, METHOD_IN_DIRECT, METHOD_OUT_DIRECT, 或METHOD_NEITHER。下面的表显示了这些方法和与之对应的能获得输入缓冲与输出缓冲的KIrp中的成员函数：Method Input Buffer Parameter OUTPUT Buffer Parameter METHOD_BUFFERED KIrp::IoctlBuffer KIrp::IoctlBuffer METHOD_IN_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_OUT_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_NEITHER KIrp::IoctlType3InputBuffer KIrp::UserBuffer 如果控制代码指明METHOD_BUFFERED，系统分配一个单一的缓冲来作为输入与输出。驱动程序必须在向输出缓冲放数据之前拷贝输入数据。驱动程序通过调用KIrp::IoctlBuffer获得缓冲地址。在完成时，I/O管理器从系统缓冲拷贝数据到提供给Ring 3级调用者使用的缓冲中。驱动程序必须在结束前存储拷贝到IRP的Information成员中的数据个数。如果控制代码不指明METHOD_IN_DIRECT或METHOD_OUT_DIRECT，则DeviceIoControl的参数呈现不同的含义。参数InputBuffer被拷贝到一个系统缓冲，这个缓冲驱动程序可以通过调用KIrp::IoctlBuffer。参数OUTPUTBuffer被映射到KMemory对象，驱动程序对这个对象的访问通过调用KIrp::Mdl来实现。对于METHOD_OUT_DIRECT，调用者必须有对缓冲的写访问权限。注意，对METHOD_NEITHER，内核只提供虚拟地址；它不会做映射来配置缓冲。虚拟地址只对调用进程有效。这里是一个用METHOD_BUFFERED的例子：首先，使用宏CTL_CODE来定义一个IOCTL代码：#define IOCTL_MYDEV_GET_FIRMWARE_REV \CTL_CODE (FILE_DEVICE_UNKNOWN,0,METHOD_BUFFERED,FILE_ANY_ACCESS)现在使用一个DeviceIoControl调用：BOOLEAN b;CHAR FirmwareRev[60];ULONG FirmwareRevSize;b = DeviceIoControl(hDevice, IOCTL_MYDEV_GET_VERSION_STRING, NULL, // no input 注意，这里放的是包含有执行操作命令的字符串指针 0, FirmwareRev, //这里是OUTPUT串指针，存放从驱动程序中返回的字符串。sizeof(FirmwareRev),& FirmwareRevSize, NULL // not overlapped I/O );如果输出缓冲足够大，设备拷贝串到里面并将拷贝的资结束设置到FirmwareRevSize中。在驱动程序中，代码看起来如下所示：const char* FIRMWARE_REV = "FW 16.33 v5";NTSTATUS MyDevice::DeviceControl( KIrp I ){ ULONG fwLength=0; switch ( I.IoctlCode() ) { case IOCTL_MYDEV_GET_FIRMWARE_REV: fwLength = strlen(FIRMWARE_REV)+1; if (I.IoctlOUTPUTBufferSize() >= fwLength) { strcpy((PCHAR)I.IoctlBuffer(),FIRMWARE_REV); I.Information() = fwLength; return I.Complete(STATUS_SUCCESS); } else { } case . . . } }
上传时间： 2013-10-17
上传用户：gai928943
The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an OUTPUT, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog OUTPUT, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.
上传时间： 2013-10-22
上传用户：taiyang250072
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its OUTPUT clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO OUTPUT is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2013-10-15
上传用户：euroford
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single OUTPUT video stream. The OUTPUT of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
针对嵌入式机器视觉系统向独立化、智能化发展的要求，介绍了一种嵌入式视觉系统--智能相机。基于对智能相机体系结构、组成模块和图像采集、传输和处理技术的分析，对国内外的几款智能相机进行比较。综合技术发展现状，提出基于FPGA+DSP模式的硬件平台，并提出智能相机的发展方向。分析结果表明，该系统设计可以实现脱离PC运行，完成图像获取与分析，并作出相应输出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding OUTPUT.
上传时间： 2013-10-24
上传用户：bvdragon
为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中，测试结果表明，调制电路能正确选相，解调电路输出数据与QDPSK调制输入数据完全一致，达到了预期的设计要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the OUTPUT data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上传时间： 2014-01-13
上传用户：qoovoop
Abstract: Many industrial/scientific/medical (ISM) band radio frequency (RF) receivers use an external Sallen-Key datafilter and a data slicer to generate the baseband digital OUTPUT. This tutorial describes the ISM-RF Baseband Calculator,which can be used to calculate the filter capacitor values and the data slicer RC components, while providing a visualexample of the baseband signals.
上传时间： 2013-11-04
上传用户：jkhjkh1982
The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an external PHY through Gigabit Media IndependentInterface (GMII) and Management Data Input/OUTPUT (MDIO) interfaces and supports tri-mode(10/100/1000 Mb/s) Ethernet. Software running from the processor cache reads and writesthrough an On-Chip Memory (OCM) interface to two FIFOs that act as buffers between thedifferent clock domains of the PPC405 OCM and the TEMAC.
上传时间： 2013-10-26
上传用户：yuzsu
