The LTC®3207/LTC3207-1 is a 600mA LED/Camera driverwhich illuminates 12 Universal LEDs (ULEDs) and onecamera fl ash LED. The ULEDs are considered universalbecause they may be individually turned on or off, setin general purpose output (GPO) mode, set to blink at aselected on-time and period, or gradate on and off at aselected gradation rate. This device also has an externalenable (ENU) pin that may be used to blink, gradate, orturn on/off the LEDs without using the I2C bus. This may beuseful if the microprocessor is in sleep or standby mode. Ifused properly, these features may save valuable memoryspace, programming time, and reduce the I2C traffi c.
上传时间： 2014-01-04
上传用户：LANCE
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2014-11-26
上传用户：erkuizhang
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
第二部分：DRAM 内存模块的设计技术..............................................................143第一章 SDR 和DDR 内存的比较..........................................................................143第二章 内存模块的叠层设计.............................................................................145第三章 内存模块的时序要求.............................................................................1493.1 无缓冲（Unbuffered）内存模块的时序分析.......................................1493.2 带寄存器（Registered）的内存模块时序分析...................................154第四章 内存模块信号设计.................................................................................1594.1 时钟信号的设计.......................................................................................1594.2 CS 及CKE 信号的设计..............................................................................1624.3 地址和控制线的设计...............................................................................1634.4 数据信号线的设计...................................................................................1664.5 电源，参考电压Vref 及去耦电容.........................................................169第五章 内存模块的功耗计算.............................................................................172第六章 实际设计案例分析.................................................................................178 目前比较流行的内存模块主要是这三种：SDR，DDR，RAMBUS。其中，RAMBUS内存采用阻抗受控制的串行连接技术,在这里我们将不做进一步探讨，本文所总结的内存设计技术就是针对SDRAM 而言(包括SDR 和DDR)。现在我们来简单地比较一下SDR 和DDR，它们都被称为同步动态内存，其核心技术是一样的。只是DDR 在某些功能上进行了改进，所以DDR 有时也被称为SDRAM II。DDR 的全称是Double Data Rate，也就是双倍的数据传输率，但是其时钟频率没有增加，只是在时钟的上升和下降沿都可以用来进行数据的读写操作。对于SDR 来说,市面上常见的模块主要有PC100/PC133/PC166,而相应的DDR内存则为DDR200(PC1600)/DDR266(PC2100)/DDR333(PC2700)。
上传时间： 2013-10-18
上传用户：宋桃子
ADAM-5510KW中FPID/PID功能块之实现及应用一、 ADAM-5510KW实现PID控制的方法1、ADAM-5510KW可以使用Multiprog软件提供的FPID和PID功能块来实现PID控制。2、ADAM-5510KW对可以使用的PID控制回路并无限制，实际上，取决于Scan Rate，ScanRate越低，则允许的PID回路越多。3、在实际应用中，流量、液位、压力、温度等等对象都可以进行控制。对于流量、液位、压力等等参数可以用传感器或变送器转换为电压/电流信号接入模拟量输入模块ADAM-5017进行采集；对于温度可以用热电偶模块ADAM-5018或热电阻模块ADAM-5013进行采集；输出的执行机构例如调节阀、风扇等等可由模拟量输出模块ADAM-5024进行控制。二、 ADAM-5510KW中如何调用FPID/PID功能块1、FPID功能块在ProconOS.fwl库中，先将库添加进Project中。
上传时间： 2013-10-12
上传用户：it男一枚
Logger iButton devices have gained a lot of popularity with researchers. Although free evaluation software is easy to use and welldocumented, the choices and inputs that need to be made can sometimes be challenging. This application note explains technicalterms that are common with temperature logger iButtons and how they relate to each other. Additionally, it presents an algorithm tohelp users choose the necessary input parameters, including the sample rate based on a user's needs and the available memory tostore the data.
上传时间： 2013-11-16
上传用户：xywhw1
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上传时间： 2013-12-25
上传用户：jkhjkh1982
S3C44BOX的BIOS。可使用的命令：help --- show help ? --- = help date --- show or set current date time --- show or set current time setweek --- set weekday clock --- show system running clock setmclk --- set system running clock setbaud ------ set baud rate ipcfg ------ show or set IP address load ------ load file to ram comload ------ load file from serial port run ------ run from sdram prog ------ program flash copy ------ copy flash from src to dst address boot ------ boot from flash backup ------ move bios to the top of flash md ------ show memory data move ------ move program from flash to sdram
上传时间： 2015-01-22
上传用户：ANRAN
This model simulates a CDMA2000 1xRTT Forward link (between Base Station and Mobile Station). In particular, it simulates the Radio Configuration 3 of a Forward Fundamental channel. The block CDMA2k: Initial settings allows you to set different parameters such as data rate, Power Control SubChannel insertion rate, spreading code index, QOSF index and the channel model.
标签： Station simulates Forward between
上传时间： 2015-03-28
上传用户：13215175592
This an adaptive receiver for a direct-sequence spread spectrum (DS-SS) system over an AWGN channel. The adaptive receiver block is modified from the LMS adaptive filter block in DSP Blockset. For DS-SS signal reception, the adaptive filter needs to have multi-rate operation. The input sample rate is equal to chip rate and the output is at symbol rate. Two rates are related by PG, processing gain
标签： direct-sequence adaptive receiver spectrum
上传时间： 2014-01-16
上传用户：D&L37
