This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This infOrmation can be usedfOr partial reconfiguration Or partial readback.
上传时间： 2013-11-05
上传用户：透明的心情
Xilinx is disclosing this user guide, manual, release note, and/Or specification (the "Documentation") to you solely fOr use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, Or transmit theDocumentation in any fOrm Or by any means including, but not limited to, electronic, mechanical, photocopying, recOrding, Or otherwise,without the priOr written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to cOrrect any errOrscontained in the Documentation, Or to advise you of any cOrrections Or updates. Xilinx expressly disclaims any liability in connection withtechnical suppOrt Or assistance that may be provided to you in connection with the InfOrmation.
上传时间： 2014-01-13
上传用户：竺羽翎2222
The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5fOr 100K gate-level units, any design with programmablelogic has a readily available 8- Or 16-bit processOr costingless than 75 cents and 32-bit processOr fOr less than $1.50.
上传时间： 2013-12-10
上传用户：zgu489
This application note describes how to build a system that can be used fOr determining theoptimal phase shift fOr a Double Data Rate (DDR) memOry feedback clock. In this system, theDDR memOry is controlled by a controller that attaches to either the OPB Or PLB and is used inan embedded microprocessOr application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO cOre that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 Or Microblaze™ microprocessOr.
上传时间： 2013-10-15
上传用户：eurofOrd
The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful fOr loadingPowerPC™ 405 (PPC405) processOr caches and/Or other data into the FPGA after the FPGAhas been configured, thus achieving partial reconfiguration. The USR_ACCESS_VIRTEX4register is programmed through the bitstream with a command that writes a series of 32-bitwOrds.
标签： USR_ACCESS PowerPC XAPP 719
上传时间： 2013-11-13
上传用户：我累个乖乖
This application note covers the design considerations of a system using the perfOrmance features of the LogiCOrE™ IP Advanced eXtensible Interface (AXI) Interconnect cOre. The design focuses on high system throughput through the AXI Interconnect cOre with F MAX and area optimizations in certain pOrtions of the design. The design uses five AXI video direct memOry access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p fOrmat, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generatOr (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) cOre capable of multiplexing Or overlaying multiple video streams to a single output video stream. The output of the OSD cOre drives the DVI video display interface on the board. PerfOrmance monitOr blocks are added to capture perfOrmance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memOry and are controlled by a MicroBlaze™ processOr. The reference system is targeted fOr the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) Or high perfOrmance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized fOr operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V Or 3.3V logic, a range of options can be deployed. This application note describes methodologies fOr interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上传时间： 2013-11-19
上传用户：yyyyyyyyyy
The fundamental problem of communication is that of reproducing at one point either exactly Or approximately a message selected at another point. Frequently the messages have meaning; that is they refer to Or are cOrrelated accOrding to some system with certain physical Or conceptual entities.
标签： 通信
上传时间： 2013-10-31
上传用户：liuxinyu2016
Xilinx is disclosing this user guide, manual, release note, and/Or specification (the “Documentation”) to you solely fOr use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, Or transmit the Documentation in any fOrm Or by any means including, but not limited to, electronic, mechanical, photocopying, recOrding, Or otherwise, without the priOr written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to cOrrect any errOrs contained in the Documentation, Or to advise you of any cOrrections Or updates. Xilinx expressly disclaims any liability in connection with technical suppOrt Or assistance that may be provided to you in connection with the InfOrmation.
标签： CPLD
上传时间： 2013-10-22
上传用户：李哈哈哈
The LogiCOrE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one Or mOre GTP transceivers to be configured using pre-definedtemplates fOr popular industry standards, Or from scratch, to suppOrt a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench fOr rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconfOrm to industry standard protocols usingpredefined templates, Or tailOr the templates fOrcustom protocols• Included protocol templates provide suppOrt fOr thefollowing specifications: AurOra, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
标签： Transceiver Virtex Wizar GTP
上传时间： 2013-10-23
上传用户：leyesome
