This article has been contributed to the TI Developer Wiki. To see the most recently updated version Or tocontribute, visit this topic at:
上传时间： 2013-11-04
上传用户：钓鳌牧马
This application repOrt discusses the design of non-invasive optical plethysmographyalso called as pulsoximeter using the MSP430FG437 Microcontroller (MCU). Thepulsoximeter consists of a peripheral probe combined with the MCU displaying theoxygen saturation and pulse rate on a LCD glass. The same sensOr is used fOr bothheart-rate detection and pulsoximetering in this application. The probe is placed on aperipheral point of the body such as a finger tip, ear lobe Or the nose. The probeincludes two light emitting diodes (LEDs), one in the visible red spectrum (660nm) andthe other in the infrared spectrum (940nm). The percentage of oxygen in the body iswOrked by measuring the intensity from each frequency of light after it transmitsthrough the body and then calculating the ratio between these two intensities.
标签： Pulsoximeter Single-Chip Des
上传时间： 2013-10-27
上传用户：黑漆漆
ARM处理器的工作模式 ARM处理器状态 ARM微处理器的工作状态一般有两种，并可在两种状态之间切换：第一种为ARM状态，此时处理器执行32位的字对齐的ARM指令；第二种为Thumb状态，此时处理器执行16位的、半字对齐的Thumb指令。在程序的执行过程中，微处理器可以随时在两种工作状态之间切换，并且，处理器工作状态的转变并不影响处理器的工作模式和相应寄存器中的内容。但ARM微处理器在开始执行代码时，应该处于ARM状态。 ARM处理器状态 进入Thumb状态：当操作数寄存器的状态位（位0）为1时，可以采用执行BX指令的方法，使微处理器从ARM状态切换到Thumb状态。此外，当处理器处于Thumb状态时发生异常（如IRQ、FIQ、Undef、AbOrt、SWI等），则异常处理返回时，自动切换到Thumb状态。 进入ARM状态：当操作数寄存器的状态位为0时，执行BX指令时可以使微处理器从Thumb状态切换到ARM状态。此外，在处理器进行异常处理时，把PC指针放入异常模式链接寄存器中，并从异常向量地址开始执行程序，也可以使处理器切换到ARM状态。ARM处理器模式 ARM微处理器支持7种运行模式，分别为：用户模式(usr)：ARM处理器正常的程序执行状态。快速中断模式(fiq)：用于高速数据传输或通道处理。外部中断模式(irq)：用于通用的中断处理。管理模式(svc)：操作系统使用的保护模式。数据访问终止模式(abt)：当数据或指令预取终止时进入该模式，可用于虚拟存储及存储保护。系统模式(sys)：运行具有特权的操作系统任务。定义指令中止模式(und)：当未定义的指令执行时进入该模式，可用于支持硬件协处理器的软件仿真。ARM处理器模式 ARM微处理器的运行模式可以通过软件改变，也可以通过外部中断或异常处理改变。大多数的应用程序运行在用户模式下，当处理器运行在用户模式下时，某些被保护的系统资源是不能被访问的。 除用户模式以外，其余的所有6种模式称之为非用户模式，或特权模式；其中除去用户模式和系统模式以外的5种又称为异常模式，常用于处理中断或异常，以及需要访问受保护的系统资源等情况。ARM寄存器 ARM处理器共有37个寄存器。其中包括：31个通用寄存器，包括程序计数器(PC)在内。这些寄存器都是32位寄存器。以及6个32位状态寄存器。 关于寄存器这里就不详细介绍了，有兴趣的人可以上网找找，很多这方面的资料。异常处理 当正常的程序执行流程发生暂时的停止时，称之为异常，例如处理一个外部的中断请求。在处理异常之前，当前处理器的状态必须保留，这样当异常处理完成之后，当前程序可以继续执行。处理器允许多个异常同时发生，它们将会按固定的优先级进行处理。当一个异常出现以后，ARM微处理器会执行以下几步操作：进入异常处理的基本步骤：将下一条指令的地址存入相应连接寄存器LR，以便程序在处理异常返回时能从正确的位置重新开始执行。将CPSR复制到相应的SPSR中。根据异常类型，强制设置CPSR的运行模式位。强制PC从相关的异常向量地址取下一条指令执行，从而跳转到相应的异常处理程序处。如果异常发生时，处理器处于Thumb状态，则当异常向量地址加载入PC时，处理器自动切换到ARM状态。 ARM微处理器对异常的响应过程用伪码可以描述为： R14_ = Return LinkSPSR_= CPSRCPSR[4:0] = Exception Mode NumberCPSR[5] = 0 ；当运行于 ARM 工作状态时If == Reset Or FIQ then；当响应 FIQ 异常时，禁止新的 FIQ 异常CPSR[6] = 1PSR[7] = 1PC = Exception VectOr Address异常处理完毕之后，ARM微处理器会执行以下几步操作从异常返回：将连接寄存器LR的值减去相应的偏移量后送到PC中。将SPSR复制回CPSR中。若在进入异常处理时设置了中断禁止位，要在此清除。
上传时间： 2013-11-15
上传用户：hanbeidang
FeaturesThe following standard features are provided.• Choice of RTOS scheduling policy1. Pre-emptive:Always runs the highest available task. Tasks of identical priOrityshare CPU time (fully pre-emptive with round robin time slicing).2. Cooperative:Context switches only occur if a task blocks, Or explicitly callstaskYIELD().• Co-routines (light weight tasks that utilise very little RAM).• Message queues• SemaphOres [via macros]• Trace visualisation ability (requires mOre RAM)• MajOrity of source code common to all suppOrted development tools• Wide range of pOrts and examples
上传时间： 2013-10-13
上传用户：13162218709
This application note describes how to decode standard DTMF tones using the minimum number of external discrete components and a PIC. The two examples use a PIC which has an 8 bit timer and either a comparatOr Or an ADC, although it can be modified fOr use on a PIC which has only digital I/O. The Appendices have example code fOr the 16C662 (with comparatOr) and 16F877 (using the ADC). As the majOrity of the Digital Signal Processing is done in software, little is required in the way of external signal conditioning. Software techniques are used to model the individual elements of a DTMF Decoder IC.
上传时间： 2013-11-21
上传用户：zhaoke2005
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their productsOr to discontinue any product Or service without notice, and advise customers to obtain the latestversion of relevant infOrmation to verify, befOre placing Orders, that infOrmation being relied onis current and complete. All products are sold subject to the terms and conditions of sale suppliedat the time of Order acknowledgement, including those pertaining to warranty, patentinfringement, and limitation of liability.
标签： Assembly Language C6000 320C
上传时间： 2013-11-12
上传用户：chens000
The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus Or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering fOrboth the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus fOr both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
标签： translating Level 9517 PCA
上传时间： 2013-12-25
上传用户：wsf950131
The PCA9540B is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, Or channels.Only one SCx/SDx channel is selected at a time, determined by the contents of theprogrammable control register.
上传时间： 2014-12-28
上传用户：nshark
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessOr low voltage 2-wire serial bus to interface with standard I2C-bus Or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering fOrboth the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus Or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
标签： 4channel transla level 9519
上传时间： 2013-11-19
上传用户：jisiwole
The PCA9541 is a 2-to-1 I2C-bus master selectOr designed fOr high reliability dual masterI2C-bus applications where system operation is required, even when one master fails Orthe controller card is removed fOr maintenance. The two masters (fOr example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled Or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.
上传时间： 2013-10-09
上传用户：3294322651
