This application note descriBes how the existing dual-port block memories in the Spartan™-IIand Virtex™ families can Be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in terms of bits per second will remain the same.
上传时间： 2014-01-24
上传用户：15527161163
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to Be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can Be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上传时间： 2013-11-01
上传用户：wojiaohs
Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes Bedifficult to determine. Programmable logic devices can Be configured in almost an infinitenumBer of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the CPLD softwareimplementation (CPLDFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPLD utilization.
上传时间： 2014-01-11
上传用户：a471778
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can Be easily expanded to target higherdensity devices. To obtain the VHDL source code descriBed in this document, go to sectionVHDL Code, page 5 for instructions.
标签： CoolRunner-II XAPP CPLD 380
上传时间： 2013-10-26
上传用户：kiklkook
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may Be provided to you in connection with the Information.
上传时间： 2013-11-11
上传用户：zwei41
The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional CPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to Be routed and shared among any of the macrocells of the functionblock.
上传时间： 2013-11-03
上传用户：1037540470
This application note descriBes how to build a system that can Be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan emBedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can Be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can Be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2014-11-26
上传用户：erkuizhang
This application note descriBes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to Be selected can Bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully synchronous interface through the ce, clk,and rst ports.
上传时间： 2013-12-14
上传用户：逗逗666
This application note shows how a Xilinx CoolRunnerTM-II CPLD can Be used as a simplelogical switch that can quickly and reliably select Between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can Be expanded by the user to perform additional operations usingthe remaining CPLD resources
标签： CoolRunner-II Xilinx XAPP CPLD
上传时间： 2013-12-16
上传用户：qwer0574
Digital cameras have Become increasingly popular over the last few years. Digital imagingtechnology has grown to new markets including cellular phones and PDA devices. With thediverse marketplace, a variety of imaging technology must Be available. Imaging technologyhas expanded to include both charge-coupled device (CCD) and CMOS image sensors.
标签： CoolRunner-II XAPP CPLD 390
上传时间： 2013-10-16
上传用户：18710733152
