Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can Be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
上传时间： 2013-11-01
上传用户：hjkhjk
The SDI standards are the predominant standards for uncompressed digital videointerfaces in the broadcast studio and video production center. The first SDI standard,SD-SDI, allowed standard-definition digital video to Be transported over the coaxial cableinfrastructure initially installed in studios to carry analog video. Next, HD-SDI wasto support high-definition video. Finally, dual link HD-SDI and 3G-SDIdoubled the bandwidth of HD-SDI to support 1080p (50 Hz and 60 Hz) and other videoformats requiring more bandwidth than HD-SDI provides.
上传时间： 2013-12-08
上传用户：liansi
XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can Be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation Between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can Be deployed. This application note descriBes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上传时间： 2013-11-06
上传用户：wentianyou
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may Be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上传时间： 2013-10-22
上传用户：aeiouetla
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should Be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions
上传时间： 2013-11-01
上传用户：xzt
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to Be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then Becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?
上传时间： 2013-10-20
上传用户：磊子226
In this paper, we discuss efficient coding and design styles using verilog. This can Beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing Behavioral models. All theseproblems are accompanied by an example to have a Better idea, and these can Be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is Beyond the scope of this paper, however,here we try to cover a few of them.
标签： Efficient Verilog Digital Coding
上传时间： 2013-11-23
上传用户：我干你啊
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can Be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has Been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have Been largely disregarded. Under theSHARP TIREP project, an attempt has Been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily Be applied to a wide range of assemblytypes and complexities.
上传时间： 2013-11-20
上传用户：pzw421125
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly Bereached, and optimize away all states and transition logic that can not Be reached.Thus, producing a highly optimal final implementation of the state machine.
标签： Synplicity Machine Verilog Design
上传时间： 2013-10-20
上传用户：苍山观海
Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot Be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
标签： Creating Machines Mentor State
上传时间： 2013-11-02
上传用户：xauthu
