msp430The LDC1312 and LDC1314 are 2- and 4-channel, 1• Easy-to-use – minimal configuration required 12-bit inductance to digital converters (LDCs) for • Measure up to 4 sensors with one IC inductive sensing solutions. With multiple channels • Multiple channels support environmental and and support for remote sensing, the LDC1312 and aging compensation LDC1314 enable the performance and reliability benefits of inductive sensing to be realized at minimal• Multi-channel remote sensing provides lowest cost and power. The products are easy to use, onlysystem cost requiring that the sensor frequency be within 1 kHz • Pin-compatible medium and high-resolution and 10 MHz to begin sensing. The wide 1 kHz to 10 options MHz sensor frequency range also enables use of very small PCB coils, further reducing sensing– LDC1312/4: 2/4-ch 12-bit LDC solution cost and size.– LDC1612/4: 2/4-ch 28
上传时间： 2016-07-22
上传用户：tongmoonsky
关于CCS调试，目标板配置advanced target configuration
标签： CCs
上传时间： 2017-05-19
上传用户：mzd1207
A simple example of audio signal processing on TMS320VC5416 USB DSK board. Main source is contained in tone.c file, memory configuration - tonecfg.cmd. Folder docs/ contains useful docmentation on board, its components and libraries. The example's configuration is based on example "tone" from Code Composer Studio's 3.1 example for 5416 DSK.
标签： DSK-example 5416 TMS 320 VC
上传时间： 2017-09-29
上传用户：wang1104014663
ansible是目前比较流行的大规模运维管理工具，使用ansible便于维护、管理大规模集群
标签： 运维管理工具
上传时间： 2018-02-05
上传用户：子非木哉
function [alpha,N,U]=youxianchafen2(r1,r2,up,under,num,deta) %[alpha,N,U]=youxianchafen2(a,r1,r2,up,under,num,deta) %该函数用有限差分法求解有两种介质的正方形区域的二维拉普拉斯方程的数值解 %函数返回迭代因子、迭代次数以及迭代完成后所求区域内网格节点处的值 %a为正方形求解区域的边长 %r1,r2分别表示两种介质的电导率 %up,under分别为上下边界值 %num表示将区域每边的网格剖分个数 %deta为迭代过程中所允许的相对误差限 n=num+1; %每边节点数 U(n,n)=0; %节点处数值矩阵 N=0; %迭代次数初值 alpha=2/(1+sin(pi/num));%超松弛迭代因子 k=r1/r2; %两介质电导率之比 U(1,1:n)=up; %求解区域上边界第一类边界条件 U(n,1:n)=under; %求解区域下边界第一类边界条件 U(2:num,1)=0;U(2:num,n)=0; for i=2:num U(i,2:num)=up-(up-under)/num*(i-1);%采用线性赋值对上下边界之间的节点赋迭代初值 end G=1; while G>0 %迭代条件：不满足相对误差限要求的节点数目G不为零 Un=U; %完成第n次迭代后所有节点处的值 G=0; %每完成一次迭代将不满足相对误差限要求的节点数目归零 for j=1:n for i=2:num U1=U(i,j); %第n次迭代时网格节点处的值 if j==1 %第n+1次迭代左边界第二类边界条件 U(i,j)=1/4*(2*U(i,j+1)+U(i-1,j)+U(i+1,j)); end if (j>1)&&(j U2=1/4*(U(i,j+1)+ U(i-1,j)+ U(i,j-1)+ U(i+1,j)); U(i,j)=U1+alpha*(U2-U1); %引入超松弛迭代因子后的网格节点处的值 end if i==n+1-j %第n+1次迭代两介质分界面（与网格对角线重合）第二类边界条件 U(i,j)=1/4*(2/(1+k)*(U(i,j+1)+U(i+1,j))+2*k/(1+k)*(U(i-1,j)+U(i,j-1))); end if j==n %第n+1次迭代右边界第二类边界条件 U(i,n)=1/4*(2*U(i,j-1)+U(i-1,j)+U(i+1,j)); end end end N=N+1 %显示迭代次数 Un1=U; %完成第n+1次迭代后所有节点处的值 err=abs((Un1-Un)./Un1);%第n+1次迭代与第n次迭代所有节点值的相对误差 err(1,1:n)=0; %上边界节点相对误差置零 err(n,1:n)=0; %下边界节点相对误差置零 G=sum(sum(err>deta))%显示每次迭代后不满足相对误差限要求的节点数目G end
标签： 有限差分
上传时间： 2018-07-13
上传用户：Kemin
DESCRIPTION The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 μs. The MSP430G2x13 and MSP430G2x53 series are ultra-low-power mixed signal microcontrollers with built-in 16- bit timers, up to 24 I/O capacitive-touch enabled pins, a versatile analog comparator, and built-in communication capability using the universal serial communication interface. In addition the MSP430G2x53 family members have a 10-bit analog-to-digital (A/D) converter. For configuration details see Table 1. Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system.
上传时间： 2018-12-25
上传用户：ygyh
pcie3.0标准规范 1. INTRODUCTION 2. TRANSACTION LAYER SPECIFICATION 3. DATA LINK LAYER SPECIFICATION 4. PHYSICAL LAYER SPECIFICATION 5. POWER MANAGEMENT 6. SYSTEM ARCHITECTURE 7. SOFTWARE INITIALIZATION AND CONFIGURATION
标签： pcie3
上传时间： 2019-07-05
上传用户：bingshi
Microsoft Visual Studio Solution File, Format Version 9.00 # Visual Studio 2005
标签： 游戏
上传时间： 2019-07-19
上传用户：cmpcmp
This work titled A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel is intended to serve as a document covering funda- mental concepts and application details related to the design of digital phase locked loop (DPLL) and its importance in wireless communication. It documents some of the work done during the last few years covering rudimentary design issues, complex implementations, and fixing configuration for a range of wireless propa- gation conditions.
上传时间： 2020-05-27
上传用户：shancjb
This research work aims at eliminating the off-chip RF SAW filters from fre- quency division duplexed (FDD) receivers. In the first approach, a monolithic passive RF filter was constructed using on-chip capacitors and bondwire inductors. The bond- wire characteristics were studied in details and the effect of mutual inductive coupling between the bondwires on the filter performance was analyzed. Based on that, a bond- wire configuration was proposed to improve the frequency response of the filter. The filter was implemented in 0.18 µm CMOS process for WCDMA applications.
标签： Interference Mitigation Techniques
上传时间： 2020-05-27
上传用户：shancjb
