This document describes part number speciÞc changes to recommended operating conditions and revised electrical speciÞcations,as applicable, from those described in the generalMPC7400 Hardware SpeciÞcations.SpeciÞcations provided in this Part Number SpeciÞcation supersede those in theMPC7400 Hardware SpeciÞcationsdated 9/99(order #: MPC7400EC/D) for these part numbers only; speciÞcations not addressed herein are unchanged. This document isfrequently updated, refer to the website at http://www.mot.com/SPS/PowerPC/ for the latest version.Note that headings and table numbers in this data sheet are not consecutively numbered. They are intended to correspond to theheading or table affected in the general hardware speciÞcation.Part numbers addressed in this document are listed in Table A. For more detailed ordering information see Table B.
上传时间： 2013-11-19
上传用户：qiaoyue
提出了一个由AT89C52单片机控制步进电机的实例。可以通过键盘输入相关数据, 并根据需要, 实时对步进电机工作方式进行设置, 具有实时性和交互性的特点。该系统可应用于步进电机控制的大多数场合。实践表明, 系统性能优于传统的步进电机控制器。关键词: 单片机; 步进电动机; 直流固态继电器; 实时控制Con trol System of Stepp ingMotor Ba sed on AT89C52 ChipM icrocomputerMENGWu2sheng, L ILiang (College of Automatization, Northwestern Polytechnical Unversity, Xipan 710072, China)ABSTRACT: A stepp ing motor control system based on AT89C52 chip microcomputer was described.The data can be inputwith keyboard, and stepp ingmotorwas controlled by these data. According to the demand, users can set the workingmodel of stepp ingmotor in real2time. This system can be widely used in stepp ing motor controlling. The p ractice showed that the performance of this system outdid the tradi tional stepp ing motor controller.KEY WORDS: Chip microcomputer; Stepp ingmotor; DCSSR; Real2time control
标签： Control System ingMot Stepp
上传时间： 2013-11-19
上传用户：leesuper
//遥控解码子程序，LC7461，用户码为11C//external interrupt0void isr_4(){ unsigned char r_count;//定义解码的个数 unsigned long use_data=0;//定义16位的用户码，只用到13位 unsigned long use_code=0;//定义16位的用户反码，只用到13位 unsigned long data=0;//定义16位数据码，包括8位数据码和反码 unsigned char data_h=0;//数据反码 unsigned char data_l=0;//数据码 _clrwdt();// _delay(7000);//7461解码，延时7000// _delay(7000);//7461解码，延时7000//_delay(7000);//7461解码，延时7000 if(remote==1) goto error; while(remote==0);//wait to high //_delay(9744);count_delay=0; while(count_delay<143); if(remote==1) goto error; /////用户码解码use_data//////////add////////////////////////// for(r_count=13;r_count>0;r_count--) { while(remote==0);//wait to high count_delay=0; while(count_delay<24);//_delay(1680); _c=remote; if(_c==1) { _lrrc(&use_data); count_delay=0; while(count_delay<32);//_delay(2200);//wait to low } else _lrrc(&use_data); } _nop(); //if(remote==1) //_delay(1680);//wait to low while(remote==1);//wait to low _nop(); ////////用户码解码finish/////////add/////////add//////// /////用户码反码解码use_code//////////add////////////////////////// for(r_count=13;r_count>0;r_count--) { while(remote==0);//wait to high count_delay=0; while(count_delay<24);//_delay(1680); _c=remote; if(_c==1) { _lrrc(&use_code); count_delay=0; while(count_delay<32);//_delay(2200);//wait to low } else _lrrc(&use_code); } _nop(); //if(remote==1) // _delay(1680);//wait to low while(remote==1);//wait to low _nop(); ////////用户码反码解码finish/////////add/////////add//////// ////数据码解码开始////data_l为用户码，data_h为数据码反码//////////// for(r_count=16;r_count>0;r_count--) { while(remote==0);//wait to high count_delay=0; while(count_delay<24);//_delay(1680); _c=remote; if(_c==1) { _lrrc(&data); count_delay=0; while(count_delay<32);//_delay(2200);//wait to low } else _lrrc(&data); } ////数据码解码结束//////////////////////////////////////////////// data_l=data; data_h=data>>8; ///用户码////// use_data>>=3; use_code>>=3; use_code=~use_code; //////// ////如果用户码等与0x11c并且数据码和数据反码都校验一致，解码成功 //if((~data_h==data_l)&&use_data==0x11c)//使用用户码 //跳过用户码 if(~data_h==data_l)//如果数据码和数据反码（取反后）相等，解码正确 { _nop(); r_data=data_l;//r_data为解出的最终数据码 } //否则解码不成功 _nop(); _nop();error: //r_data=nocode; _nop(); _nop(); _nop();}
上传时间： 2014-03-27
上传用户：shenlan
用单片机配置FPGA—PLD设计技巧 Configuration/Program Method for Altera Device Configure the FLEX Device You can use any Micro-Controller to configure the FLEX device–the main idea is clocking in ONE BITof configuration data per CLOCK–start from the BIT 0The total Configuration time–e.g. 10K10 need 15K byte configuration file•calculation equation–10K10* 1.5= 15Kbyte–configuration time for the file itself•15*1024*8*clock = 122,880Clock•assume the CLOCK is 4MHz•122,880*1/4Mhz=30.72msec
上传时间： 2013-10-09
上传用户：a67818601
摘 要 瞬态仿真领域的许多工作需要获得可视化数据, 仿真电路不能将输出参数绘制成图形时研究工作将受到很大影响. 而权威电路仿真软件PSpice 在这个方面不尽如人意. 本文提出了一种有效的解决办法: 通过MATLAB 编程搭建一个PSpice 与MATLAB 的数据接口,使PSpice输出数据文件可以导入到MATLAB中绘制图形. 这令我们能够很方便地获得数据的规律以有效地分析仿真结果, 这项技术对于教学和工程实践都有比较实际的帮助.关键词: 瞬态仿真 仿真程序 PSpice MATLAB 可视化数据The Data Transfer from Pspice to MATLABWu hao Ning yuanzhong Liang yingAbstract Many works in the area of transient simulation has shown how a emulator such asPSpice can be interfaced to an control analysis package such as MATLAB to get viewdata. Thepaper describes how such interfaces can be made using the MATLAB programming. The platformas a typical platform will solve the problem that PSpice software sometimes can not draw the datato a picture. It can make us find the rule from numerous data very expediently, so we can analyzethe outcome of the simulation. And it also can be used in the field of education.Keywords Transient Simulation Emulator PSpice MATLAB Viewdata1 引言科学研究和工程应用常需要进行电路仿真 PSpice可进行直流 交流 瞬态等基本电路特性分析 也可进行蒙托卡诺 MC 统计分析 最坏情况 Wcase 分析 优化设计等复杂电路特性分析 它是国际上仿真电路的权威软件 而MATLAB的主要特点有 高效方便的矩阵和数组运算 编程效率高 结构化面向对象 方便的绘图功能 用户使用方便 工具箱功能强大 两者各有着重点 两种软件结合应用 对研究工作有很重要的意义香港理工大学Y. S. LEE 等人首先将PSpice和MATLAB结合 开发了电力电子电路优化用的CAD 程序MATSPICE[6] 将两者相结合的关键在于 如何用MATLAB 获取PSpice的仿真数据 对此参考文献 6 里没有详细叙述 本文着重说明用MATLAB 读取PSpice仿真数据的具体方法本论文利用MATLAB对PSpice仿真出的数据处理绘制出后者无法得到或是效果不好的仿真图形 下面就两者结合使用的例子 进行具体说明
上传时间： 2013-10-20
上传用户：wuchunzhong
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
上传时间： 2013-11-11
上传用户：zhouli
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上传时间： 2014-08-16
上传用户：adada
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2013-10-15
上传用户：euroford
The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) processor caches and/or other data into the FPGA after the FPGAhas been configured, thus achieving partial reconfiguration. The USR_ACCESS_VIRTEX4register is programmed through the bitstream with a command that writes a series of 32-bitwords.
标签： USR_ACCESS PowerPC XAPP 719
上传时间： 2013-11-13
上传用户：我累个乖乖
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
