We all know the benefits of using FieldProgrammable Gate Arrays (FPGAs): no NRE, nominimum order quantities, and faster time-tomarket.In an ideal world, designs would never needto be changed because of design errors, but we allknow that sometimes this is necessary.
上传时间： 2013-11-04
上传用户：leixinzhuo
6小时学会labview, labview Six Hour Course – Instructor Notes This zip file contains material designed to give students a working knowledge of labview in a 6 hour timeframe. The contents are: Instructor Notes.doc – this document. labviewIntroduction-SixHour.ppt – a PowerPoint presentation containing screenshots and notes on the topics covered by the course. Convert C to F (Ex1).vi – Exercise 1 solution VI. Convert C to F (Ex2).vi – Exercise 2 solution subVI. Thermometer-DAQ (Ex2).vi – Exercise 2 solution VI. Temperature Monitor (Ex3).vi – Exercise 3 solution VI. Thermometer (Ex4).vi – Exercise 4 solution subVI. Convert C to F (Ex4).vi – Exercise 4 solution subVI. Temperature Logger (Ex4).vi – Exercise 4 solution VI. Multiplot Graph (Ex5).vi – Exercise 5 solution VI. Square Root (Ex6).vi – Exercise 6 solution VI. State Machine 1 (Ex7).vi – Exercise 7 solution VI. The slides can be presented in two three hour labs, or six one hour lectures. Depending on the time and resources available in class, you can choose whether to assign the exercises as homework or to be done in class. If you decide to assign the exercises in class, it is best to assign them in order with the presentation. This way the students can create VI’s while the relevant information is still fresh. The notes associated with the exercise slide should be sufficient to guide the students to a solution. The solution files included are one possible solution, but by no means the only solution.
标签： labview
上传时间： 2013-10-13
上传用户：zjwangyichao
在研究传统家用燃气报警器的基础上，以ZigBee协议为平台，构建mesh网状网络实现网络化的智能语音报警系统。由于传感器本身的温度和实际环境温度的影响，传感器标定后采用软件补偿方法。为了减少系统费用，前端节点采用半功能节点设备，路由器和协调器采用全功能节点设备，构建mesh网络所形成的家庭内部报警系统，通过通用的电话接口连接到外部的公用电话网络，启动语音模块进行报警。实验结果表明，在2.4 GHz频率下传输，有墙等障碍物的情况下，节点的传输距离大约为35 m，能够满足家庭需要，且系统工作稳定，但在功耗方面仍需进一步改善。 Abstract: On the basis of studying traditional household gas alarm system, this paper proposed the platform for the ZigBee protocol，and constructed mesh network to achieve network-based intelligent voice alarm system. Because of the sensor temperature and the actual environment temperature, this system design used software compensation after calibrating sensor. In order to reduce system cost, semi-functional node devices were used as front-end node, however, full-function devices were used as routers and coordinator，constructed alarm system within the family by building mesh network，connected to the external public telephone network through the common telephone interface, started the voice alarm module. The results indicate that nodes transmit about 35m in the distance in case of walls and other obstacles by 2.4GHz frequency transmission, this is able to meet family needs and work steadily, but still needs further improvement in power consumption.
上传时间： 2013-10-30
上传用户：swaylong
为了能够满足基站易于选址、优质快速的建站要求和易维护、低成本、高可靠的运行要求，本文对以方舱来实现一体化结构基站做出一番探讨。从系统设计的观点阐述了移动通信高性能基站天线设计的几个关键问题，介绍了智能天线技术在基站中的应用，并且用HFSS软件仿真了一种新型的对称阵子天线，该天线驻波比小于2的带宽可以达到60%，具有良好的宽频带特性。 Abstract: In order to meet the station construction requirement of easy site selection and fast base station， and meet the operational requirement of easy maintenance， low cost and high reliability， this paper discussed the unified architecture base station using shelter. Several key problems of high performance mobile communication base station antenna were illustrated from the view of system design， the application of smart antenna in base station was also introduced. And a novel dipole antenna was simulated by using HFSS， the VSWR of the antenna is less than 2， and the bandwidth was reach to 60%. So it has good broadband properties.
上传时间： 2013-11-20
上传用户：linlin
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上传时间： 2013-11-21
上传用户：不懂夜的黑
Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. Programmable logic devices can be configured in almost an infinitenumber of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the CPLD softwareimplementation (CPLDFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPLD utilization.
上传时间： 2014-01-11
上传用户：a471778
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
标签： CoolRunner-II XAPP CPLD 380
上传时间： 2013-10-26
上传用户：kiklkook
This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to be selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully synchronous interface through the ce, clk,and rst ports.
上传时间： 2013-12-14
上传用户：逗逗666
为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中，测试结果表明，调制电路能正确选相，解调电路输出数据与QDPSK调制输入数据完全一致，达到了预期的设计要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上传时间： 2013-10-28
上传用户：jyycc
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2014-01-24
上传用户：s363994250
