All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
MPC7400 Part Number SpeciÞcationThis document describes part number speciÞc changes to recommended operating conditions and revised electrical speciÞcations,as applicable, from those described in the generalMPC7400 Hardware SpeciÞcations.SpeciÞcations provided in this Part Number SpeciÞcation supersede those in theMPC7400 Hardware SpeciÞcationsdated 9/99(order #: MPC7400EC/D) for these part numbers only; speciÞcations not addressed herein are unchanged. This document isfrequently updated, refer to the website at http://www.mot.com/SPS/PowerPC/ for the latest version.Note that headings and table numbers in this data sheet are not consecutively numbered. They are intended to correspond to theheading or table affected in the general hardware speciÞcation.
上传时间： 2014-12-28
上传用户：huyahui
This document describes part number speciÞc changes to recommended operating conditions and revised electrical speciÞcations,as applicable, from those described in the generalMPC7400 Hardware SpeciÞcations.SpeciÞcations provided in this Part Number SpeciÞcation supersede those in theMPC7400 Hardware SpeciÞcationsdated 9/99(order #: MPC7400EC/D) for these part numbers only; speciÞcations not addressed herein are unchanged. This document isfrequently updated, refer to the website at http://www.mot.com/SPS/PowerPC/ for the latest version.Note that headings and table numbers in this data sheet are not consecutively numbered. They are intended to correspond to theheading or table affected in the general hardware speciÞcation.Part numbers addressed in this document are listed in Table A. For more detailed ordering information see Table B.
上传时间： 2013-11-19
上传用户：qiaoyue
//芯片资料请到www.elecfans.com查找 //DS1820 C51 子程序//这里以11.0592M晶体为例，不同的晶体速度可能需要调整延时的时间//sbit DQ =P2^1;//根据实际情况定义端口 typedef unsigned char byte;typedef unsigned int word; //延时void delay(word useconds){ for(;useconds>0;useconds--);} //复位byte ow_reset(void){ byte presence; DQ = 0; //pull DQ line low delay(29); // leave it low for 480us DQ = 1; // allow line to return high delay(3); // wait for presence presence = DQ; // get presence signal delay(25); // wait for end of timeslot return(presence); // presence signal returned} // 0=presence, 1 = no part //从 1-wire 总线上读取一个字节byte read_byte(void){ byte i; byte value = 0; for (i=8;i>0;i--) { value>>=1; DQ = 0; // pull DQ low to start timeslot DQ = 1; // then return high delay(1); //for (i=0; i<3; i++); if(DQ)value|=0x80; delay(6); // wait for rest of timeslot } return(value);} //向 1-WIRE 总线上写一个字节void write_byte(char val){ byte i; for (i=8; i>0; i--) // writes byte, one bit at a time { DQ = 0; // pull DQ low to start timeslot DQ = val&0x01; delay(5); // hold value for remainder of timeslot DQ = 1; val=val/2; } delay(5);} //读取温度char Read_Temperature(void){ union{ byte c[2]; int x; }temp; ow_reset(); write_byte(0xCC); // Skip ROM write_byte(0xBE); // Read Scratch Pad temp.c[1]=read_byte(); temp.c[0]=read_byte(); ow_reset(); write_byte(0xCC); //Skip ROM write_byte(0x44); // Start Conversion return temp.x/2;}
上传时间： 2013-11-03
上传用户：hongmo
针对使用硬件描述语言进行设计存在的问题，提出一种基于FPGA并采用DSP Builder作为设计工具的数字信号处理器设计方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ设计流程，设计了一个12阶FIR 低通数字滤波器，通过Quartus 时序仿真及嵌入式逻辑分析仪SignalTapⅡ硬件测试对设计进行了验证。结果表明，所设计的FIR 滤波器功能正确，性能良好。 Abstract: Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
上传时间： 2013-11-17
上传用户：lo25643
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their productsor to discontinue any product or service without notice, and advise customers to obtain the latestversion of relevant information to verify, before placing orders, that information being relied onis current and complete. All products are sold subject to the terms and conditions of sale suppliedat the time of order acknowledgement, including those pertaining to warranty, patentinfringement, and limitation of liability
上传时间： 2013-12-26
上传用户：凌云御清风
CCStudio Platinum Edition is available in a number of ways. Existingcustomers who are up-to-date with their subscription service withTexas Instruments will receive their update automatically on a CD inthe mail. New customers who wish to purchase a copy of CCStudioPlatinum Edition can order TMDSCCSALL-1 starting May 23, 2005. A120-day Trial version will be also be available on CDROM startingJuly 11, 2005. Users may order the CDROM of the 120-day free copy
上传时间： 2014-12-28
上传用户：gououo
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上传时间： 2013-10-22
上传用户：ztj182002
为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中，测试结果表明，调制电路能正确选相，解调电路输出数据与QDPSK调制输入数据完全一致，达到了预期的设计要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上传时间： 2014-01-13
上传用户：qoovoop
Abstract: Standard PCB design and mounting processes can adversely influence MEMS inertial sensors.This application note contains guidelines for the layout, soldering, and mounting of MEMS inertialsensors in LGA packages in order to reduce stresses and improve functionality.
上传时间： 2014-01-15
上传用户：sjb555
