This is the Xilinx Dual Processor Reference Designs suite. The designs illustrate a few differentdual-core architectures based on the Microblaze™ and PowerPC™ processors. The designsillustrate various concepts described in the Xilinx White Paper WP262 titled, “DesigningMultiprocessor Systems in Platform Studio”. There are simple software applications includedwith the reference designs that show various forms of interaction between the two processors.
上传时间： 2013-10-29
上传用户：旭521
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2014-11-26
上传用户：erkuizhang
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a Microblaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
摘要：本文简要介绍了Xilinx最新的EDK9.1i和ISE9.1i等工具的设计使用流程，最终在采用65nm工艺级别的Xilinx Virtex-5 开发板ML505 上同时设计实现了支持TCP/IP 协议的10M/100M/1000M 的三态以太网和千兆光以太网的SOPC 系统,并对涉及的关键技术进行了说明。关键词：FPGA；EDK；SOPC；嵌入式开发；EMAC；Microblaze 本研究采用业界最新的Xilinx 65ns工艺级别的Virtex-5LXT FPGA 高级开发平台，满足了对于建造具有更高性能、更高密度、更低功耗和更低成本的可编程片上系统的需求。Virtex-5以太网媒体接入控制器(EMAC)模块提供了专用的以太网功能，它和10/100/1000Base-T外部物理层芯片或RocketIOGTP收发器、SelectIO技术相结合，能够分别实现10M/100M/1000M的三态以太网和千兆光以太网的SOPC 系统。
上传时间： 2013-10-28
上传用户：DE2542
uC/OS-II Notes from Nohau Corporation The code associated with this readme.txt file is provided "as is". The code was written with the intention of creating a functional RTOS demo for the Nohau evaluation boards that can run a Microblaze core. You can use this code for any and all of your projects, as you see fit. Nohau Corporation does not warrant that the code is bug-free, and will provide no support for this RTOS port.
标签： Corporation associated provided readme
上传时间： 2013-12-27
上传用户：tzl1975
Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not Microblaze.
标签： Spartan drives This perphrials
上传时间： 2014-05-29
上传用户：SimonQQ
本程序用xilinx EDK9.1运行，通过Microblaze软核，实现在sparton——3e板卡上的按键及开关的控制，通过RS－232与超级终端进行通信。
上传时间： 2016-10-02
上传用户：qiao8960
赛灵思的FPGA，设计的软核Microblaze示例
上传时间： 2017-03-13
上传用户：libinxny
原创作品，真正可用的超小型 bootloader。将存于norflash里的elf文件装入ram运行，比xilinx提供的bootloader好用多了，至少可以节省你1周的时间. 嵌入式系统用 edk powerpc 或 Microblaze 通用
标签：
上传时间： 2017-07-10
上传用户：a6697238
EGO1 是依元素科技基于 Xilinx Artix-7 FPGA 研发的便携式数模混合基础教 学平台。EGO1 配备的 FPGA (XC7A35T-1CSG324C)具有大容量高性能等特点， 能实现较复杂的数字逻辑设计；在 FPGA 内可以构建 Microblaze 处理器系统， 可进行 SoC 设计。该平台拥有丰富的外设，以及灵活的通用扩展接口。
上传时间： 2017-10-14
上传用户：wlwl
