ALLEGRO15.X学习与的用（下）
上传时间： 2013-06-28
上传用户：1136815862
Orcad 使用
标签： Orcad
上传时间： 2013-06-28
上传用户：lepoke
stc 单片机ISP程序
上传时间： 2013-09-05
上传用户：a471778
著名的游戏开发库Allegro4.2.0 for DELPHI.rar
上传时间： 2013-09-06
上传用户：海陆空653
cadence_virtuoso软件新手入门教材，用户手册。
标签： cadence_virtuoso 软件 入门教
上传时间： 2013-09-09
上传用户：hoperingcong
* DESCRIPTION: DDS design BY PLD DEVICES.\r\n *\r\n * AUTHOR: Sun Yu\r\n *\r\n * HISTORY: 12/06/2002 \r\n *
标签： DESCRIPTION DEVICES design DDS
上传时间： 2013-09-09
上传用户：jokey075
上传时间： 2013-11-03
上传用户：taox
allegro16.3教程1
上传时间： 2013-11-16
上传用户：urgdil
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
标签： Efficient Verilog Digital Coding
上传时间： 2013-11-22
上传用户：han_zh
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上传时间： 2014-12-23
上传用户：xinhaoshan2016
