This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is CONTROLled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is CONTROLled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2013-10-15
上传用户：euroford
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are CONTROLled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is CONTROLled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is CONTROLled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2014-11-26
上传用户：erkuizhang
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are CONTROLled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
在Multisim 10软件环境下，设计一种由运算放大器构成的精确可控矩形波信号发生器，结合系统电路原理图重点阐述了各参数指标的实现与测试方法。通过改变RC电路的电容充、放电路径和时间常数实现了占空比和频率的调节，通过多路开关投入不同数值的电容实现了频段的调节，通过电压取样和同相放大电路实现了输出电压幅值的调节并提高了电路的带负载能力，可作为频率和幅值可调的方波信号发生器。Multisim 10仿真分析及应用电路测试结果表明，电路性能指标达到了设计要求。 Abstract: Based on Multisim 10， this paper designed a kind of rectangular-wave signal generator which could be CONTROLled exactly composed of operational amplifier， the key point was how to implement and test the parameter indicators based on the circuit diagram. The duty and the frequency were adjusted by changing the time constant and the way of charging and discharging of the capacitor， the width of frequency was adjusted by using different capacitors provided with multiple switch， the amplitude of output voltage was adjusted by sampling voltage and using in-phase amplifier circuit，the ability of driving loads was raised， the circuit can be used as squarewave signal generator whose frequency and amplitude can be adjusted. The final simulation results of Multisim 10 and the tests of applicable circuit show that the performance indicators of the circuit meets the design requirements.
上传时间： 2014-01-21
上传用户：shen007yue
Lachesis an IRCRPG combat engine written in a combination of C and C++. The combat engine is being written for a specific RPG, but most of the project should be useful to IRCRPGs in general. It includes a native interface to the IRC protocol to allow it to act as an IRC bot, for such uses as dice rolling and acting as a remote-CONTROLled client (RPG NPC perhaps).
标签： combat engine combination Lachesis
上传时间： 2014-01-26
上传用户：firstbyte
pdnMesh is an automatic mesh generator and solver for Finite Element problems. It will also do post-processing to generate contour plots and Postscript printouts. GUI support using GTK or MFC (Win32) is available. The problem definition can be done in any form and given to pdnMesh as an input data file. Drawing Exchange Format (DXF) files can be directly imported to pdnmesh. The quality and the coarseness of the mesh can be CONTROLled by giving input parameters.
标签： automatic generator problems pdnMesh
上传时间： 2013-12-19
上传用户：cuibaigao
yright 2002 Cygnal Integrated Products, Inc. // // Filename: LIION_BC_MAIN.c // Target Device: 8051F300 // Created: 11 SEP 2002 // Created By: DKC // Tool chain: KEIL Eval C51 // // This is a stand alone battery charger for a Lithium ION battery. // It utilizes a buck converter, CONTROLled by the on-chip 8-bit PWM, // to provide constant current followed by constant voltage battery charge.
标签： LIION_BC_MAIN Integrated Filename Products
上传时间： 2013-12-23
上传用户：牧羊人8920
ATmega8 taillight circuitAn assembly language program that generates 5 different static patterns with switching from pattern-to-pattern CONTROLled by the depression of one push-button switch (S2).
标签： taillight circuitAn generates different
上传时间： 2014-01-12
上传用户：wanghui2438
机顶盒界面源代码： ## Avoid the so-called SINGAPPL to be initialized at runtime ## Used when the tuner is CONTROLled externally by I2C and ## the PIDs forced to some specific values.
标签： initialized the so-called SINGAPPL
上传时间： 2013-12-08
上传用户：lixinxiang
