The MIPS32® 4KEm™ core from MIPS® Technologies is a member of the MIPS32 4KE™ processor core family. It is a high-performance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications. The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor. It is highly portable across processes, and can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user products. The 4KEm core is ideally positioned to support new products for emerging segments of the digital consumer, network, systems, and information management markets, enabling new tailored solutions for embedded applications.
标签： MIPS 8482 Technologies 174
上传时间： 2014-12-22
上传用户：semi1981
After the successful global introduction during the past decade of the second generation (2G) digital mobile communications systems, it seems that the third generation (3G) Universal Mobile Communication System (UMTS) has finally taken off, at least in some regions. The plethora of new services that are expected to be offered by this system requires the development of new paradigms in the way scarce radio resources should be managed. The Quality of Service (QoS) concept, which introduces in a natural way the service differentiation and the possibility of adapting the resource consumption to the specific service requirements, will open the door for the provision of advanced wireless services to the mass market.
标签： the introduction successful generation
上传时间： 2013-12-30
上传用户：qq21508895
DaVinci HD CPLD Firmware Resources 这是TI原装开发板DM6467原理图的 CPLD的VHDL代码，是Spectrum Digital, Inc刚开发出来的！ CPLD Firmware Project CPLD Firmware Project (Version 6).
标签： CPLD Resources Firmware DaVinci
上传时间： 2016-11-27
上传用户：爱死爱死
DM6467_DaVinciHD_EVM原装开发板原理图和使用说明，用cadence打开。TI的开发板制造商Spectrum Digital公司刚设计的。达芬奇的开发资料目前很少的！
标签： DaVinciHD_EVM 6467 DM 开发板原理图
上传时间： 2016-11-27
上传用户：qq521
MPEG-2 has 7 distinct parts as well. The first part is the Systems section which defines the container format and the Transport Streams that are designed to carry the digital video and audio over ATSC and DVB. The Program Stream defines the container format for lossy compression on optical disks, DVDs and SVCDs.
标签： the distinct Systems defines
上传时间： 2014-07-02
上传用户：奇奇奔奔
数字处理与电机控制 一、数字处理单元 近代科技技术有一个很重要的趋势，就是数字化，由于微电子技术的快速发展，带动了数字化科技的落实，从最早的4位处理器，到现在各式各样百花齐放的处理器或微控器，进而牵引了诸多数字化的技术与理论，如﹝电机﹞数字控制、数字相机﹝digital camera﹞、数字通讯，汽车工业等，无一不影响生活周遭，以下便针对市面上常见的组件做简略地介绍。
上传时间： 2013-12-23
上传用户：asddsd
The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x generation of digital signal processor (DSP) controllers, are part of the TMS320C2000 platform of fixed-point DSPs. The 240xA devices offer the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While code-compatible with the existing C24x DSP controller devices, the 240xA offers increased processing performance (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device Summary section for device-specific features.
标签： TMS 320 generation 240
上传时间： 2013-12-16
上传用户：GavinNeko
DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上传时间： 2014-11-01
上传用户：l254587896
《FPGA数字电子系统设计与开发实例导航》的配套光盘，Verilog编写，USB、I2C、MAC的接口设计-"FPGA digital electronic system design and development examples navigation" matching discs, Verilog prepared, USB, I2C, the MAC interface design
上传时间： 2017-02-10
上传用户：himbly
This document describes how to switch to and program the unisersal serial bus (USB) analog phase-locked loop (APLL) on the C5506/C5507/C5509A devices. Example assembly programs for programming and switching to and from the APLL are also provided in the attached zip file. It is assumed that the reader is familiar with the use and operation of the C5506/C5507/C5509A USB digital phase-locked loop (DPLL) and C55x™ Digital Signal Processor (DSP) IDLE procedures.
标签： describes unisersal document phase-lo
上传时间： 2014-01-13
上传用户：hustfanenze
