ACPR (adjacent channel power ratio), AltCPR (alternatechannel power ratio), and noise are important performancemetrics for digital communication systems thatuse, for example, WCDMA (wideband code division multipleaccess) modulation. ACPR and AltCPR are bothmeasures of spectral regrowth. The power in the WCDMAcarrier is measured using a 5MHz measurement bandwidth;see Figure 1. In the case of ACPR, the total powerin a 3.84MHz bandwidth centered at 5MHz (the carrierspacing) away from the center of the outermost carrier ismeasured and compared to the carrier power. The resultis expressed in dBc. For AltCPR, the procedure is thesame, except we center the measurement 10MHz awayfrom the center of the outermost carrier.
上传时间： 2013-11-02
上传用户：maricle
Java Clock is a FREE Java applet used to display a clock on your Web pages. You can display either analog or digital clock. The full source code of this applet is also available (visit my home page to download it). You may use this applet on your Web pages WITHOUT paying me fee or royalty as long as credit is given (a link to my home page is enough).
标签： display Java applet either
上传时间： 2014-01-12
上传用户：woshiayin
A C++ framework for creating Linux and Windows communications applications that contain Dialogic/Intel NetStructure products. Includes media and network classes (analog, digital, SIP, H323), multithreaded event handling, distributed app support.
标签： communications applications framework creating
上传时间： 2014-01-11
上传用户：mhp0114
pic mcu code:This application note describes the design and implementation of a USB Mass Storage Device (MSD) using a Secure Digital card, which should prove useful to developers of USB mass storage solutions. This application may be used as a stand-alone MSD or as a Secure Digital/Multimedia Card (SD/MMC) reader/ writer interface.
标签： implementation application describes Storage
上传时间： 2014-11-23
上传用户：天诚24
This project is created using the Keil ARM CA Compiler. The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already configured to show the PWM output signal on PORT3.0 and PORT3.1 This ARM Example may be debugged using only the uVision Simulator and your PC--no additional hardware or evaluation boards are required. The Simulator provides cycle-accurate simulation of all on-chip peripherals of the ADuC7000 device series. You may create various input signals like digital pulses, sine waves, sawtooth waves, and square waves using signal functions which you write in C. Signal functions run in the background in the simulator within timing constraints you configure. In this example, several signal functions are defined in the included Startup_SIM.INI file.
标签： the Analyzer Compiler project
上传时间： 2013-12-19
上传用户：Yukiseop
常用MATLAP程序，包括通信DSP常用算法。希望对大家用帮助 matlap example,including communivation digital signal process.
上传时间： 2015-06-18
上传用户：coeus
dvbsnoop is a DVB/MPEG stream analyzer program. The program can be used to sniff, monitor, debug, dump or view DVB/MPEG/DSM-CC/MHP stream information (digital television or data broadcasts) sent via satellite, cable or terrestrial.
标签： program dvbsnoop analyzer monitor
上传时间： 2013-12-14
上传用户：zhangyi99104144
This application report introduces and describes an MP3 /AAC audio player for use with the TMS320C54x(TM) digital signal processor (DSP) devices. This audio player is based on Reference Framework Level 3 (RF3). Reference Framework for eXpressDSP(TM) Software is a start-ware for developing applications that use DSP/BIOS(TM) and the TMS320(TM) DSP AlgorithmStandard.
标签： application introduces describes report
上传时间： 2014-05-25
上传用户：x4587
硬件设计指南(PDF格式)，主要包括：Low Voltage Interfaces；Grounding in Mixed Signal Systems；Digital Isolation Techniques； Power Supply Noise Reduction and Filtering； Dealing with High Speed Logic
上传时间： 2015-08-31
上传用户：阿四AIR
Verilog and VHDL状态机设计，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.
上传时间： 2013-12-19
上传用户：change0329
