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variable-Frequency

  • 一个基于Java的小游戏

    一个基于Java的小游戏,有助于帮助理解Java中Class之间的数据传递以及public, private variable的不同用法。

    标签: Java 小游戏

    上传时间: 2016-10-02

    上传用户:jcljkh

  • Circular Convolution of two equal-length vectors. Highlights that circular convolution in the time d

    Circular Convolution of two equal-length vectors. Highlights that circular convolution in the time domain is the effectively the same as element-by-element multiplication in the frequency domain.

    标签: equal-length Convolution convolution Highlights

    上传时间: 2014-01-22

    上传用户:aig85

  • WB_BPSK_Analysis.rar:BPSK modulation and link analysis of UWB monocycle and doublet waveforms.Revise

    WB_BPSK_Analysis.rar:BPSK modulation and link analysis of UWB monocycle and doublet waveforms.Revised 1/2/05-JC.This m file plots the time and frequency waveforms for BPSK 1st and 2nd derivative equations used in UWB system analysis.

    标签: WB_BPSK_Analysis modulation and monocycle

    上传时间: 2016-11-12

    上传用户:邶刖

  • JAVA music player. Project Homepage : http://www.javazoom.net/jlgui/jlgui.html Developer

    JAVA music player. Project Homepage : http://www.javazoom.net/jlgui/jlgui.html Developer Homepage : http://sourceforge.net/project/?group_id=1344 ----------------------------------------------------- To launch jlGui just doucle click under jlGui2.0.jar. If nothing appear then edit jlGui.bat (or jlGui.sh) script and setup JLGUI_HOME variable and launch the script. To play local file : Left click on "Eject" button. To play remote file/stream : Right click on "Eject" Button. To fill in playlist : Edit default.m3u file before launching jlGui.

    标签: jlgui Developer Homepage javazoom

    上传时间: 2016-11-16

    上传用户:wpwpwlxwlx

  • PRINCIPLE: The UVE algorithm detects and eliminates from a PLS model (including from 1 to A componen

    PRINCIPLE: The UVE algorithm detects and eliminates from a PLS model (including from 1 to A components) those variables that do not carry any relevant information to model Y. The criterion used to trace the un-informative variables is the reliability of the regression coefficients: c_j=mean(b_j)/std(b_j), obtained by jackknifing. The cutoff level, below which c_j is considered to be too small, indicating that the variable j should be removed, is estimated using a matrix of random variables.The predictive power of PLS models built on the retained variables only is evaluated over all 1-a dimensions =(yielding RMSECVnew).

    标签: from eliminates PRINCIPLE algorithm

    上传时间: 2016-11-27

    上传用户:凌云御清风

  • script for generting transmit waveforms in a minimum shift keying, a form of continuous phase freque

    script for generting transmit waveforms in a minimum shift keying, a form of continuous phase frequency shift keying

    标签: continuous generting waveforms transmit

    上传时间: 2016-11-30

    上传用户:ANRAN

  • MATLAB Code for Optimal Quincunx Filter Bank Design Yi Chen July 17, 2006 This file introduces t

    MATLAB Code for Optimal Quincunx Filter Bank Design Yi Chen July 17, 2006 This file introduces the MATLAB code that implements the two algorithms (i.e., Algorithms 1 and 2 in [1], or Algorithms 4.1 and 4.2 in [2]) used for the construction of quincunx filter banks with perfect reconstruction, linear phase, high coding gain, certain vanishing moments properties, and good frequency selectivity. The code can be used to design quincunx filter banks with two, three, or four lifting steps. The SeDuMi Matlab toolbox [3] is used to solve the second-order cone programming subproblems in the two algorithms, and must be installed in order for this code to work.

    标签: introduces Quincunx Optimal MATLAB

    上传时间: 2014-01-15

    上传用户:cc1

  • DDR SDRAM控制器的VHDL源代码

    DDR SDRAM控制器的VHDL源代码,含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.

    标签: SDRAM VHDL DDR 控制器

    上传时间: 2014-11-01

    上传用户:l254587896

  • *** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 2

    *** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a ** PIC16C54 8-bit CMOS single chip microcomputer ** Revsied Version 2.0 (4/2/92). ** ** Part use = PIC16C54-XT/JW ** Note: 1) All timings are based on a reference crystal frequency of 2MHz ** which is equivalent to an instruction cycle time of 2 usec. ** 2) Address and literal values are read in octal unless otherwise ** specified.

    标签: Microchip Routines Sample WRITE

    上传时间: 2013-12-27

    上传用户:ljmwh2000

  • We address the problem of predicting a word from previous words in a sample of text. In particular,

    We address the problem of predicting a word from previous words in a sample of text. In particular, we discuss n-gram models based on classes of words. We also discuss several statistical algorithms for assigning words to classes based on the frequency of their co-occurrence with other words. We find that we are able to extract classes that have the flavor of either syntactically based groupings or semantically based groupings, depending on the nature of the underlying statistics.

    标签: predicting particular previous address

    上传时间: 2016-12-26

    上传用户:xfbs821