VERILOG HDL 实际工控项目源码\r\n开发工具 altera quartus2
上传时间： 2013-09-05
上传用户：youmo81
Cadence Verilog Language and Simulation
标签： Simulation Language Cadence Verilog
上传时间： 2013-09-06
上传用户：yl1140vista
System will automatically delete the directory
标签： automatically directory System delete
上传时间： 2013-09-09
上传用户：toyoad
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
标签： Efficient Verilog Digital Coding
上传时间： 2013-11-22
上传用户：han_zh
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions
上传时间： 2013-10-17
上传用户：tb_6877751
Introduce High-Speed Digital System Design.
标签： High-Speed Digital Design System
上传时间： 2013-10-20
上传用户：gps6888
Xilinx公司推出的DSP设计开发工具System Generator是在Matlab环境中进行建模，是DSP高层系统设计与Xilinx FPGA之间实现的“桥梁”。在分析了FPGA传统级设计方法的基础上，提出了基于System Generator的系统级设计新方法，并应用新方法设计验证了一套数字下变频系统，通过仿真和实验结果验证了该方法的有效性和准确性。
上传时间： 2013-11-18
上传用户：小草123
数电Verilog相关课件
上传时间： 2013-10-23
上传用户：wangzeng
MeTech Verilog例程。
上传时间： 2013-11-05
上传用户：wpwpwlxwlx
用Verilog实现8255芯片功能
上传时间： 2013-10-31
上传用户：sunjet
