The above title is not happenstance and was arrived at afterconsiderable deliberation. As a linear IC manufacturer, it isour goal to encourage users to design and build switchingregulators. A problem is that while everyone agrees thatworking switching regulators are a good thing, everyonealso agrees that they are difficult to get working. Switchingregulators, with their high efficiency and small size, areincreasingly desirable as overall package sizes shrink.Unfortunately, switching regulators are also one of themost difficult linear circuits to design. Mysterious modes,sudden, seemingly inexplicable failures, peculiar regulationcharacteristics and just plain explosions are commonoccurrences. Diodes conduct the wrong way. Things gethot that shouldn’t. Capacitors act like resistors, fusesdon’t blow and transistors do. The output is at ground, andthe ground terminal shows volts of noise.
标签： Regulators Switching Poets for
上传时间： 2013-12-19
上传用户：奇奇奔奔
Abstract: This application note describes how to build, debug, and run applications on the on-board MAXQ622microcontroller to interface with the DS8005 dual smart card interface. This is demonstrated in both IAREmbedded Workbench and the Rowley CrossWorks IDE, using sample code provided with the kit.
上传时间： 2013-10-29
上传用户：ddddddd
为解决当前计算机串行通讯接口只有USB，难以满足旧型号设备或某些单片机要求RS232通讯的问题，设计出两款RS232/USB电路。采用CH341A与MAX223集成电路芯片构建标准9线RS232/USB通用接口转换器，无需编程。采用CH341A与PIC16F877A构建单片机与计算机之间的USB通讯电路，软件遵循RS232通讯协议，硬件进行电平转换。实际使用表明，这两款产品与计算机端Windows 操作系统下的串口应用程序完全兼容，且通讯过程中无握手失败现象。 Abstract: To solve the problem that current computer serial communication only with USB interface can not satisfy with the old type equipments or MCU to communicate with RS232， two kinds of RS232/USB circuit were designed.CH341A and MAX223 integrated circuit chips were used to create a standard 9-line RS232/USB universal interface convertor without programme. CH341A and PIC16F877A chips were adopted to build the USB communication circuit between computers and MCU. The software follows RS232 communication protocol， and the hardware converts electrical levels. Actual practices indicate that the two manufactures are compatible with serial application program of Windows operation system completely，and get avoid of handshake lost.
上传时间： 2013-11-03
上传用户：siying
伟福仿真器系统概述 本仿真器系统由仿真主机+仿真头、MULT1A用户板、实验板、开关电源等组成。本系统的特点是： 1．主机+仿真头的组合，通过更换不同型号的仿真头即可对各种不同类型的单片机进行仿真，是一种灵活的多CPU仿真系统。采用主机+POD组合的方式，更换POD，可以对各种CPU进行仿真。本仿真器主机型号为E2000/S，仿真头型号为POD8X5X（可仿真51系列8X5X单片机）。 2．双平台，具有DOS版本和WINDOWS版本，后者功能强大，中/英文界面任选，用户源程序的大小不再有任何限制，支持ASM，c，PLM语言混合编程，具有项目管理功能，为用户的资源共享、课题重组提供强有力的手段。支持点屏显示，用鼠标左键点一下源程序中的某一变量，即可显示该变量的数值。有丰富的窗口显示方式，多方位，动态地显示仿真的各种过程，使用极为便利。本操作系统一经推出，立即被广大用户所喜爱。 3．双工作模式①.软件模拟仿真(不要仿真器也能模拟仿真)。②硬件仿真。 4．双CPU结构，100％不占用户资源。全空间硬件断点，不受任何条件限制，支持地址、数据、外部信号、事件断点、支持实时断点计数、软件运行时间统计。 5．双集成环境编辑、编译、下载、调试全部集中在一个环境下。多种仿真器，多类CPU仿真全部集成在一个环境下。可仿真51系列，196系列，PIC系列，飞利蒲公司的552、LPC764、DALLAS320，华邦438等51增强型CPU。为了跟上形势，现在很多工程师需要面对和掌握不同的项目管理器、编辑器、编译器。他们由不同的厂家开发，相互不兼容，使用不同的界面，学习使用都很吃力。伟福WINDOWS调试软件为您提供了一个全集成环境，统一的界面，包含一个项目管理器，一个功能强大的编辑器，汇编Make、Build和调试工具并提供千个与第三方编译器的接口。由于风格统一，大大节省了您的精力和时间。 6．强大的逻辑分析仪综合调试功能。逻辑分析仪由交互式软件菜单窗口对系统硬件的逻辑或时序进行同步实时采样，并实时在线调试分析，采集深度32K(E2000/L)，最高时基采样频率达20MHz，40路波形，可精确实时反映用户程序运行时的历史时间。系统在使用逻辑分析仪时，除普通的单步运行、键盘断点运行、全速硬件断点运行外，还可实现各种条件组合断点如：数据、地址、外部控制信号、CPU内部控制信号、程序区间断点等。由于逻辑仪可以直接对程序的执行结果进行分析，因此极大地便利于程序的调试。随着科学技术的发展，单片机通讯方面的运用越来越多。在通讯功能的调试时，如果通讯不正常，查找原因是非常耗时和低效的，您很难搞清楚问题到底在什么地方，是波特率不对，是硬件信道有问题，是通讯协仪有问题，是发方出错还是收方出错。有了逻辑仪，情况则完全不一样，用它可以分别或者同时对发送方、接收方的输入或者输出波形进行记录、存储、对比、测量等各种直观的分析，可以将实际输出通讯报文的波形与源程序相比较，可立即发现问题所在，从而极大地方便了调试。 7．强大的追踪器功能追踪功能以总线周期为单位，实时记录仿真过程中CPU发生的总线事件，其触发条件方式同逻辑分析仪。追踪窗口在仿真停止时可收集显示追踪的CPU指令记忆信息，可以以总线反汇编码模式、源程序模式对应显示追踪结果。屏幕窗口显示波形图最多追踪记忆指令32K并通过仿真器的断点、单步、全速运行或各种条件组合断点来完成追踪功能。总线跟踪可以跟踪程序的运行轨迹。可以统计软件运行时间。
上传时间： 2013-11-01
上传用户：xiehao13
前言智能仪表课采用了《单片机原理与接口技术》作为教材，这是一门实践性极强的课程，理论和实验教学的有机结合，是提高教学质量的唯一途径。为密切配合理论教学，针对SICElab赛思开放式综合实验/仿真系统，我们编写了配套的实验教材。SICElab赛思开放式综合实验/仿真系统采用了符合单片机开发过程的“仿真式”组合设计思想，使得所有的实验模块及CPU资源均全力对用户开放，从而充分满足“验证式”→“模仿式”→“探索式”→“开发式”的由浅入深的各种实验要求。赛思开放式综合实验/仿真系统采用伟福G6W仿真器,为用户提供了一个大集成软件环境，统一的界面，包含一个项目管理器，一个功能强大的编辑器，汇编Make、build和调试工具并提供一个与第三方编译器的接口，具有DOS/WINDOWS双平台,仿真器与实验平台分离，采用“仿真”方式进行实验，同时，允许进行脱机运行工作，所以，实验过程是与实际开发过程完全一致的。仿真器使用的是双“CPU”架构方式，100%资源出让，100%实时，100%无条件硬件断点，可满足学生实验，毕业设计，参加电子竞争，教师科研所需。第一章简单介绍了赛思开放式综合实验/仿真系统的组成（包括实验平台、仿真器、软件支持、开关电源），实验内容，实验方式，支持器件等。第二章选编了二十例验证式实验，包括实验平台操作，连接仿真器、PC机，利用DOS和WINDOWS平台软硬件结合的实验，按由浅入深原则排列。第三章选编了十六例模仿和探索开发式实验。教师和学生可根据课时和具体情况选择实验内容，或自行设计新的实验内容。由于课时所限，有的实验可让学生在课后开放实验室时完成，以提高学生动手能力，提高教学质量，培养学生创新精神。附录一介绍了综合实验平台各模块的电路图，附录二是实验平台键盘操作仿真方法说明。由于时间匆忙，加上编者水平有限，难免有错漏之处，请读者不吝赐教。
上传时间： 2013-10-22
上传用户：sunshie
汇编器在微处理器的验证和应用中举足轻重，如何设计通用的汇编器一直是研究的热点之一。本文提出了一种开放式的汇编器系统设计思想，在汇编语言与机器语言间插入中间代码CMDL（code mapping description language）语言，打破汇编语言与机器语言的直接映射关系，由此建立起一套描述汇编语言与机器语言的开放式映射体系。基于此开放式映射体系开发了一套汇编器系统，具有较高层次上的通用性和可移植性。【关键词】指令集，CMDL，汇编器，开放式 Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【关键词】instruction set, symbol table, assembler, lexical analysis, retargetability
上传时间： 2013-10-10
上传用户：meiguiweishi
1 /**————————————————————2 〖说明〗I2C总线驱动程序(用两个普通IO模拟I2C总线)3 包括100Khz(T=10us)的标准模式(慢速模式)选择，4 和400Khz(T=2.5us)的快速模式选择，5 默认11.0592Mhz的晶振。6 〖文件〗PCF8563T.C ﹫2001/11/2 77 〖作者〗龙啸九天 c51@yeah.net http://www.c51bbs.co /8 〖修改〗修改建议请到论坛公布 http://www.c51bbs.co m9 〖版本〗V1.00A Build 080310 —————————————————————*/1112 #ifndef SDA13 #define SDA P0_014 #define SCL P0_115 #endif1617 extern uchar SystemError;1819 #define uchar unsigned char20 #define uint unsigned int21 #define Byte unsigned char22 #define Word unsigned int23 #define bool bit24 #define true 125 #define false 02627 #define SomeNOP(); _nop_();_nop_();_nop_();_nop_();2829 /**--------------------------------------------------------------------------------30 调用方式：void I2CStart(void) ﹫2001/07/0 431 函数说明：私有函数，I2C专用32 ---------------------------------------------------------------------------------*/33 void I2CStart(void)34 {35 EA=0;36 SDA=1; SCL=1; SomeNOP();//INI37 SDA=0; SomeNOP(); //START38 SCL=0;39 }4041 /**--------------------------------------------------------------------------------42 调用方式：void I2CStop(void) ﹫2001/07/0 443 函数说明：私有函数，I2C专用44 ---------------------------------------------------------------------------------*/45 void I2CStop(void)46 {47 SCL=0; SDA=0; SomeNOP(); //INI48 SCL=1; SomeNOP(); SDA=1; //STOP49 EA=1;50 }5152 /**--------------------------------------------------------------------------------53 调用方式：bit I2CAck(void) ﹫2001/07/0 454 函数说明：私有函数，I2C专用，等待从器件接收方的应答55 ---------------------------------------------------------------------------------*/56 bool WaitAck(void)57 {58 uchar errtime=255;//因故障接收方无ACK，超时值为255。59 SDA=1;SomeNOP();60 SCL=1;SomeNOP();61 while(SDA) {errtime--; if (!errtime) {I2CStop();SystemError=0x11;return false;}}62 SCL=0;63 return true;
上传时间： 2014-04-11
上传用户：xg262122
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2013-10-15
上传用户：euroford
This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserializer (SerDes) interface. This application note describes how to set up thespecific clocking structure required for the SerDes interface and the constraints to be added tothe UCF file. This reference system is complete with a standalone software application to testsome of the main features of this core, including access to registers, DMA capabilities, transmitand receive in loopback mode. This reference system is targeted for the ML300 evaluationboard.
上传时间： 2013-11-01
上传用户：truth12
