本系统以单片机为核心 , 构建了由光电二极管检测和比较 , 方位角和高度角双轴机械跟踪定位系统组成的自动控制装置 , 设计出一套自动使太阳能电池板保持与太阳光垂直的自动跟踪系统。在晴天检测时能自动跟踪太阳并实时回存正确数据 , 消除因季节变化而产生的积累误差 , 在阴天时能自动引用晴天时的位置 , 控制精度高 , 具有广泛的应用潜力。实现了追踪太阳的效果 , 达到提高发电效率的目的。
上传时间： 2013-10-26
上传用户：lanhuaying
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
标签： synchronous Emulating serial
上传时间： 2014-01-31
上传用户：z1191176801
The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29
上传时间： 2013-11-04
上传用户：as275944189
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
The MC68HC05K0 is a low cost, low pin countsingle chip microcomputer with 504 bytes of userROM and 32 bytes of RAM. The MC68HC05K0 isa member of the 68HC05K series of devices whichare available in 16-pin DIL or SOIC packages.It uses the same CPU as the other devices in the68HC05 family and has the same instructions andregisters. Additionally, the device has a 15-stagemulti-function timer and 10 general purposebi-directional I/0 lines. A mask option is availablefor software programmable pull-downs on all ofthe I/O pins and four of the pins are capable ofgenerating interrupts.The device is ideally suited for remote-controlkeyboard applications because the pull-downs andthe interrupt drivers on the port pins allowkeyboards to be built without any externalcomponents except the keys themselves. There isno need for external pull-up or pull-down resistors,or diodes for wired-OR interrupts, as these featuresare already designed into the device.
上传时间： 2014-01-24
上传用户：zl5712176
《现代微机原理与接口技术》实验指导书 TPC-H实验台C语言版 1.实验台结构1）I / O 地址译码电路如上图1所示地址空间280H～2BFH共分8条译码输出线：Y0～Y7 其地址分别是280H～287H、288H～28FH、290H～297H、298H～29FH、2A0H～2A7H、2A8H～2AFH、2B0H～2B7H、2B8H～2BFH，8根译码输出线在实验台I/O地址处分别由自锁紧插孔引出供实验选用（见图2）。 2) 总线插孔采用“自锁紧”插座在标有“总线”区引出数据总线D7～D0；地址总线A9～A0，读、写信号IOR、IOW；中断请求信号IRQ ；DMA请求信号DRQ1；DMA响应信号DACK1 及AEN信号，供学生搭试各种接口实验电路使用。3) 时钟电路如图-3所示可以输出1MHZ 2MHZ两种信号供A/D转换器定时器/计数器串行接口实验使用。图34) 逻辑电平开关电路如图-4所示实验台右下方设有8个开关K7～K0，开关拨到“1”位置时开关断开，输出高电平。向下打到“0”位置时开关接通，输出低电平。电路中串接了保护电阻使接口电路不直接同＋5V 、GND相连，可有效地防止因误操作误编程损坏集成电路现象。图 4 图 55) L E D 显示电路如图-5所示实验台上设有8个发光二极管及相关驱动电路（输入端L7～L0），当输入信号为“1” 时发光，为“0”时灭6) 七段数码管显示电路如图-6所示实验台上设有两个共阴极七段数码管及驱动电路，段码为同相驱动器，位码为反相驱动器。从段码与位码的驱动器输入端（段码输入端a、b、c、d、e、f、g、dp，位码输入端s1、 s2）输入不同的代码即可显示不同数字或符号。
上传时间： 2013-11-22
上传用户：sssnaxie
通用的多电源总线，如VME、VXI 和PCI 总线，都可提供功率有限的3.3V、5V 和±12V（或±24V）电源，如果在这些系统中添加设备（如插卡等），则需要额外的3.3V或5V电源，这个电源通常由负载较轻的-12V电源提供。图1 电路，将-12V 电压升压到15.3V（相对于-12V 电压），进而得到3.3V 的电源电压，输出电流可达300mA。Q2 将3.3V 电压转换成适当的电压（-10.75V）反馈给IC1 的FB 引脚，PWM 升压控制器可提供1W 的输出功率，转换效率为83%。整个电路大约占6.25Cm2的线路板尺寸，适用于依靠台式PC机电源供电，需要提供1W输出功率的应用，这种应用中，由于-12V总线电压限制在1.2W以内，因此需要保证高于83%的转换效率。由于限流电阻（RSENSE）将峰值电流限制在120mA，N 沟道MOSFET（Q1）可选用廉价的逻辑电平驱动型场效应管，R1、R2 设置输出电压（3.3V 或5V）。IC1 平衡端（Pin5）的反馈电压高于PGND引脚（Pin7）1.25V，因此：VFB = -12V + 1.25V = - 10.75V选择电阻R1后，可确定：I2 = 1.25V / R1 = 1.25V / 12.1kΩ = 103μA可由下式确定R2：R2 = （VOUT - VBE）/ I2 =（3.3V - 0.7V）/ 103μA = 25.2 kΩ图1 中，IC1 的开关频率允许通过外部电阻设置，频率范围为100kHz 至500kHz，有利于RF、数据采集模块等产品的设计。当选择较高的开关频率时，能够保证较高的转换效率，并可选用较小的电感和电容。为避免电流倒流，可在电路中增加一个与R1串联的二极管。
上传时间： 2013-10-17
上传用户：jixingjie
单片机开发中除必要的硬件外，同样离不开软件，我们写的汇编语言源程序要变为CPU可以执行的机器码有两种方法，一种是手工汇编，另一种是机器汇编，目前已极少使用手工汇编的方法了。机器汇编是通过汇编软件将源程序变为机器码，用于MCS-51 单片机的汇编软件有早期的A51，随着单片机开发技术的不断发展，从普遍使用汇编语言到逐渐使用高级语言开发，单片机的开发软件也在不断发展，Keil 软件是目前最流行开发MCS-51 系列单片机的软件，这从近年来各仿真机厂商纷纷宣布全面支持Keil 即可看出。Keil 提供了包括C编译器、宏汇编、连接器、库管理和一个功能强大的仿真调试器等在内的完整开发方案，通过一个集成开发环境（uVision）将这些部份组合在一起。运行Keil 软件需要Pentium 或以上的CPU，16MB或更多RAM、20M 以上空闲的硬盘空间、WIN98、NT、WIN2000、WINXP等操作系统。掌握这一软件的使用对于使用51 系列单片机的爱好者来说是十分必要的，如果你使用C 语言编程，那么Keil 几乎就是你的不二之选（目前在国内你只能买到该软件、而你买的仿真机也很可能只支持该软件），即使不使用C 语言而仅用汇编语言编程，其方便易用的集成环境、强大的软件仿真调试工具也会令你事半功倍。我们将通过一些实例来学习Keil 软件的使用，在这一部份我们将学习如何输入源程序，建立工程、对工程进行详细的设置，以及如何将源程序变为目标代码。图1 所示电路图使用89C51 单片机作为主芯片，这种单片机性属于MCS-51 系列，其内部有4K 的FLASH ROM,可以反复擦写，非常适于做实验。89C51 的P1 引脚上接8 个发光二极管，P3.2~P3.4 引脚上接4 个按钮开关，我们的第一个任务是让接在P1 引脚上的发光二极管依次循环点亮。 一、Keil 工程的建立首先启动Keil 软件的集成开发环境，这里假设读者已正确安装了该软件，可以从桌面上直接双击uVision 的图标以启动该软件。UVison启动后，程序窗口的左边有一个工程管理窗口，该窗口有3 个标签，分别是Files、Regs、和Books，这三个标签页分别显示当前项目的文件结构、CPU 的寄存器及部份特殊功能寄存器的值（调试时才出现）和所选CPU 的附加说明文件，如果是第一次启动Keil，那么这三个标签页全是空的。
上传时间： 2013-12-26
上传用户：liulinshan2010
The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.
上传时间： 2013-10-22
上传用户：taiyang250072
