介绍了当前普通标记机控制系统现状及其存在缺点，给出气动标记机及相频修正PWM模式的工作原理。采用ATmega16单片机和USB转换RS232接口器件CH341T实现驱动控制系统与PC的实时通讯，标记控制系统可升级到USB接口。采用基于ATmega16的相频修正PWM替换555振荡电路产生的PWM，可直接通过软件调整PWM信号。使用达林顿三极管TIP122替代直流继电器驱动高频电磁阀，使得电磁阀驱动电路简单，成本低廉。该控制系统已成功应用于气动标记机。 Abstract: In this paper,the actuality and demerit of the common gas marking machine control systems are described.The operation principle of the gas marking machine and the phase and frequency correct PWM of ATmega16is introduced.The real-time communication between the driving control system and PC by CH341T which its function is translated USB to RS232is realized,the control systems is updated grade to USB interface.The PWM signal can be adjustable by software for the555surge circuit was substituted by the phase and frequency.The high frequency electromagnetic value’s driving circuit by DC relay is replaced by TIP122,therefore,the circuit is become simple and the cost cheap.The control systems has been widely used in gas marking machine.
上传时间： 2013-10-18
上传用户：1427796291
介绍了采用ATmega48单片机实现三相无刷直流电机控制器的方法。利用Atmega48获得带死区的脉宽调制（PWM）、霍尔传感器的换相处理、正弦驱动信号的产生和电机转速的控制等功能。采用该方法的优点是所需的外围器件少，成本低。 Abstract: The method of 3-phase brushless DC motor control based on ATmega48 is presented in this paper.The system uses ATmega48 to generate PWM signals with dead-time, hall sensors signals commutation，sine driving signal and rotational speed of motor.Using this method，the needed external devices are few, the cost is low.
上传时间： 2013-12-09
上传用户：330402686
FEATURES400 MSPS internal clock speedIntegrated 10-bit DAC32-bit tuning wordPhase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output)Excellent dynamic performance>75 dB SFDR @ 160 MHz (±100 kHz offset) AOUTSerial I/O control1.8 V power supplySoftware and hardware controlled power-down48-lead TQFP/EP packageSupport for 5 V input levels on most digital inputsPLL REFCLK multiplier (4× to 20×)Internal oscillator; can be driven by a single crystalPhase modulation capabilityMultichip synchronization
上传时间： 2014-12-04
上传用户：axin881314
MCU(单片机)对可控硅的控制:交流市电控制――ＭＣＵ对可控硅的控制 郭江辛 07-23-03在用可控硅对交流市电控制中，主要注意以下几个方面：一， 同步信号 （弄不好都会产生不均匀的斩波，控制白炽灯表现为灯闪）1) 清楚同步信号在交流周期中的位置,最好在交流零点选取.在一些阻容降压对MCU 供电电路中,最好直接在交流电源两端取同步信号（过零点）,以避免计算阻容产生的象移(PHASE SHIFT)2) 同步信号要稳定二， 控制信号 （弄不好则可控硅不能通，或一直通）1） 可控硅断路时，可控硅控制极（GATE）最好是开路，没有开极的MCU可加如下电路：
上传时间： 2014-05-05
上传用户：comer1123
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2013-10-15
上传用户：euroford
针对传统集成电路（ASIC）功能固定、升级困难等缺点，利用FPGA实现了扩频通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核实现NCO模块，在下变频模块调用了硬核乘法器并引入CIC滤波器进行低通滤波，给出了DQPSK解调的原理和实现方法，推导出一种简便的引入?仔/4固定相移的实现方法。采用模块化的设计方法使用VHDL语言编写出源程序，在Virtex-II Pro 开发板上成功实现了整个系统。测试结果表明该系统正确实现了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
上传时间： 2013-11-06
上传用户：liu123
为了在CDMA系统中更好地应用QDPSK数字调制方式，在分析四相相对移相（QDPSK)信号调制解调原理的基础上，设计了一种QDPSK调制解调电路，它包括串并转换、差分编码、四相载波产生和选相、相干解调、差分译码和并串转换电路。在MAX+PLUSⅡ软件平台上，进行了编译和波形仿真。综合后下载到复杂可编程逻辑器件EPM7128SLC84-15中，测试结果表明，调制电路能正确选相，解调电路输出数据与QDPSK调制输入数据完全一致，达到了预期的设计要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上传时间： 2014-01-13
上传用户：qoovoop
The Maxim Integrated 71M6541-DB REV 3.0 Demo Board is a demonstration board for evaluating the 71M6541 device for single-phase electronic energy metering applications in conjunction with the Remote Sensor Inter-face. It incorporates a 71M6541 integrated circuit, a 71M6601 Remote Interface IC, peripheral circuitry such as a serial EEPROM, emulator port, and on-board power supply. A serial to USB converter allows communication to a PC through a USB port. The Demo Board allows the evaluation of the 71M6541 energy meter chip for measurement accuracy and overall system use.
上传时间： 2013-11-06
上传用户：雨出惊人love
Abstract: This article explains the recent trend in heart-rate and fitness monitors to go wireless toeliminate cables to allow free movement, and allow convenient data collection without the need to plug intheir devices. It details a typical wireless system, using the MAX1472 crystal-referenced phase-lockedloop (PLL) VHF/UHF transmitter.
标签： Heart-RateFitness Monitors Wireless Go
上传时间： 2013-11-11
上传用户：xiaowei314
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2014-11-26
上传用户：erkuizhang
