MAXQUSBJTAGOW评估板软件:关键特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
标签： MAXQUSBJTAGOW 评估板 软件
上传时间： 2013-11-23
上传用户：truth12
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上传时间： 2013-12-07
上传用户：bruce
WP369可扩展式处理平台-各种嵌入式系统的理想解决方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
上传时间： 2013-10-18
上传用户：cursor
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上传时间： 2013-11-20
上传用户：pzw421125
Abstract: This application note presents an overview of electronic margining and its value in detectingpotential system failures before a product ships from the factory. It is a calibration method that effectivelypredicts and allows adjustments to improve product quality. Margining also can be used to sort productsinto performance levels, allowing premium products to be sold at premium prices. We discuss thedownside of sorting and suggest alternative ways to segregate products.
上传时间： 2014-01-22
上传用户：lhw888
This directory contains 3 file system modules: - file system ISO9660 iso9660.c iso9660.h - file system FAT12/16 fat.c fat.h - file system FAT32 fat32.c fat32.h file.c and file.h contains all high levels functions/macro/definition for your application. fs_variable.c contains all definitions of variables that can be shared with the all file systems. config.h must contain the definition of the file system used by your application.
标签： 9660 file system directory
上传时间： 2015-03-15
上传用户：脚趾头
he LPC932 can be used to create a Pulse Width Modulated PWM signal. That s an analog signal, with only 2 discrete levels, for example 0V and 5V and a constant period. The current value of this signal at a certain poiTnt of time is proportional to its Duty Cycle. That s the High Time during one period divided by the period. It can also be calculated as the average value during a particular period. That means after low pass filtering, (e.g. RC circuit) the signal becomes analog, with an actual value controlled by the microcontroller. The PWM functionality enables the LPC932 to control for example the speed of DC motors or the brightness of electric lighting.
标签： signal Modulated analog create
上传时间： 2015-05-14
上传用户：CHINA526
Welcome to MS4W, the no fuss installer for setting up MapServer on Microsoft Windows platforms. The purpose of this package is to allow all levels of MapServer users to quickly install a working environment for MapServer development on Windows. It is also an environment for packaging and distributing MapServer applications.
标签： MapServer Microsoft installer platforms
上传时间： 2015-05-31
上传用户：黄华强
SharpZipLib之前叫做NZipLib，完全由 C# 开发的压缩库，支持Zip, GZip, Tar and BZip2 ，为2007年8月最新0852release版的源文件和文档说明！ Changes for v0.85.2 release Minor tweaks for CF, ZipEntryFactory and ZipFile. Fix for zip testing and Zip64 local header patching. FastZip revamped to handle file attributes on extract + other fixes Null ref in path filter fixed. Extra data handling fixes Revamped build and conditional compilation handling Many bug fixes for Zip64. Minor improvements to C# samples. ZIP-1341 Non ascii zip password handling fix. ZIP-355 Fix for zip compression problem at low levels
标签： SharpZipLib NZipLib
上传时间： 2015-12-11
上传用户：84425894
