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  • Three-input Majority Voter -- The entity declaration is followed by three alternative architectures

    Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.

    标签: architectures Three-input declaration alternative

    上传时间: 2013-12-27

    上传用户:liansi

  • Swfdec still is development software, but has also followed a rigid no-crashes-allowed policy. I b

    Swfdec still is development software, but has also followed a rigid no-crashes-allowed policy. I believe it s stable enough now to be installed as a default plugin for people that can live with occasional crashes of their browser. But don t blame me if it does crash. File a bug at https://bugs.freedesktop.org/enter_bug.cgi?product=swfdec

    标签: no-crashes-allowed development followed software

    上传时间: 2016-04-14

    上传用户:franktu

  • PRINCIPLE: Removal of the row mean from each row, followed by division of the row by the respective

    PRINCIPLE: Removal of the row mean from each row, followed by division of the row by the respective row standard deviation.

    标签: the row respective PRINCIPLE

    上传时间: 2016-11-27

    上传用户:z1191176801

  • JPEG Image compression using IJG standards followed

    JPEG Image compression using IJG standards followed

    标签: compression standards followed Image

    上传时间: 2017-07-11

    上传用户:z754970244

  • Verilog Coding Style for Efficient Digital Design

      In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.

    标签: Efficient Verilog Digital Coding

    上传时间: 2013-11-22

    上传用户:han_zh

  • 降压升压型控制器简化手持式产品的DC/DC转换器设计

      A number of conventional solutions have been available forthe design of a DC/DC converter where the output voltageis within the input voltage range—a common scenarioin Li-Ion battery-powered applications—but none werevery attractive until now. Conventional topologies, suchas SEPIC or boost followed by buck, have numerousdisadvantages, including low effi ciency, complex magnetics,polarity inversion and/or circuit complexity/cost. TheLTC®3785 buck-boost controller yields a simple, effi cient,low parts-count, single-converter solution that is easyto implement, thus avoiding the drawbacks associatedwith traditional solutions.

    标签: DC 降压 升压型 控制器

    上传时间: 2013-10-21

    上传用户:ljt101007

  • XAPP122 - Spartan-XL FPGA的Express配置

    Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui

    标签: Spartan-XL Express XAPP FPGA

    上传时间: 2014-12-28

    上传用户:hewenzhi

  • ZBT SRAM控制器参考设计,xilinx提供VHDL代码

    ZBT SRAM控制器参考设计,xilinx提供VHDL代码 Description:   Contains the following files     readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform:   All Installation/Use:   Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.

    标签: xilinx SRAM VHDL ZBT

    上传时间: 2013-11-24

    上传用户:31633073

  • HITECH与电脑的通信协议

    1 Communication Protocol (Computer as master)   The communication protocol describes here allows your computer to access 4096 internal registers (W0000-W4095) and 1024 internal relays (B0000-B1023) in the Workstation..   1.1 Request Message Format   Request message is a command message to be sent from the computer to the Workstation. The data structure of request message is shown below. Note that numbers are always in hexadecimal form and converted into ASCII characters. For example, Workstation unit number 14 will appear in the message as character 0(30h) followed by character E(45h); a BCC of 5Ah will appear in the message as character 5(35h) followed by character A(41h). 

    标签: HITECH 电脑 通信协议

    上传时间: 2013-10-28

    上传用户:cxl274287265

  • XAPP122 - Spartan-XL FPGA的Express配置

    Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui

    标签: Spartan-XL Express XAPP FPGA

    上传时间: 2015-01-02

    上传用户:nanxia