关于VeriLog中的可综合语句和不可综合语句的汇总介绍
标签： VeriLog
上传时间： 2013-11-27
上传用户：squershop
VeriLog经典教程
上传时间： 2013-10-31
上传用户：waitingfy
宇闻着VeriLog数字系统设计教程word版
上传时间： 2013-11-03
上传用户：zhang_yi
宇闻着VeriLog数字系统设计教程word版
上传时间： 2013-10-11
上传用户：angle
《VeriLog HDL程序设计与实践》系统讲解了VeriLog HDL的基本语法和高级应用技巧，对于每个知识点都按照开门见山、自顶向下的方式来组织内容，在介绍相关知识点之前，先告诉读者其出现的背景、本质特征以及应用场景，让读者不仅掌握基本语法，还能够获得深层次理解。从结构上讲，《VeriLog HDL程序设计与实践》以VeriLog HDL的各方面开发为主线，遵照硬件应用系统开发的基本步骤和思路进行详细讲解，并穿插介绍ISE开发工具的操作技巧与注意事项，具备很强的可读性、指导性和实用性。
上传时间： 2013-11-21
上传用户：silenthink
夏宇闻VeriLog经典教程
上传时间： 2013-10-21
上传用户：zhangyi99104144
This Application Note covers the basics of how to use VeriLog as applied to ComplexProgrammable Logic Devices. Various combinational logic circuit examples, such asmultiplexers, decoders, encoders, comparators and adders are provided. Synchronous logiccircuit examples, such as counters and state machines are also provided.
上传时间： 2013-11-11
上传用户：y13567890
One of the most misunderstood constructs in the VeriLog language is the nonblockingassignment. Even very experienced VeriLog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant VeriLog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how VeriLog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid VeriLog simulation race conditions
上传时间： 2013-11-01
上传用户：xzt
In this paper, we discuss efficient coding and design styles using VeriLog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
标签： Efficient VeriLog Digital Coding
上传时间： 2013-11-23
上传用户：我干你啊
本文简单讨论并总结了VHDL、VeriLog，System VeriLog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
标签： VeriLog VeriLog System VHDL
上传时间： 2014-03-03
上传用户：zhtzht
