系统start-up 定时器• 为了让振荡器能够稳定起振所需要的延时时间。• 其时间为1024 个振荡器振荡周期。制程和温度漂移• 因RC 振荡器的频率与内建振荡电容值有关，而此电容值与制程参数有关，所以不同的MCU 会表现出不一致性。在固定电压和温度下，振荡频率漂移范围约±25%。• 对于同一颗MCU(与制程漂移无关)，其振荡频率会对工作电压和工作温度产生漂移。其对工作电压和工作温度所产生的漂移，可参考HOLTEK 网站上提供的相关资料。EMI/EMS(EMC)注意事项• ROSC 位置应尽量接近OSC1 引脚，其至OSC1 的连线应最短。• CS 可以提高振荡器的抗干扰能力，其与MCU OSC1 和GND 的连线应最短。• RPU 在确定系统频率之后，量产时建议不要接，因为其fSYS/4 频率输出会干扰到OSC1
上传时间： 2014-01-20
上传用户：yyyyyyyyyy
典型的MCU/DSP/UP复位电源监控，外部看门狗专用电路。
上传时间： 2013-10-11
上传用户：LANCE
The PL2303 USB to Serial adapter is your smart and convenient accessory forconnecting RS-232 serial devices to your USB-equipped Windows host computer. Itprovides a bridge connection with a standard DB 9-pin male serial port connector inone end and a standard Type-A USB plug connector on the other end. You simplyattach the serial device onto the serial port of the cable and plug the USB connectorinto your PC USB port. It allows a simple and easy way of adding serial connectionsto your PC without having to go thru inserting a serial card and traditional portconfiguration.This USB to Serial adapter is ideal for connecting modems, cellular phones, PDAs,digital cameras, card readers and other serial devices to your computer. It providesserial connections up to 1Mbps of data transfer rate. And since USB does not requireany IRQ resource, more devices can be attached to the system without the previoushassles of device and resource conflicts.Finally, the PL-2303 USB to Serial adapter is a fully USB Specification compliantdevice and therefore supports advanced power management such as suspend andresume operations as well as remote wakeup. The PL-2303 USB Serial cable adapteris designed to work on all Windows operating systems.
上传时间： 2013-11-01
上传用户：ghostparker
上传时间： 2014-05-05
上传用户：刘江林1420
CCStudio Platinum Edition is available in a number of ways. Existingcustomers who are up-to-date with their subscription service withTexas Instruments will receive their update automatically on a CD inthe mail. New customers who wish to purchase a copy of CCStudioPlatinum Edition can order TMDSCCSALL-1 starting May 23, 2005. A120-day Trial version will be also be available on CDROM startingJuly 11, 2005. Users may order the CDROM of the 120-day free copy
上传时间： 2014-12-28
上传用户：gououo
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
标签： Solutions Analog Xilinx FPGAs
上传时间： 2013-11-01
上传用户：a67818601
Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)
标签： Solutions Analog Altera FPGAs
上传时间： 2013-11-08
上传用户：虫虫虫虫虫虫
In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting challenge that often extends, rather thanshortens, design time. As today's designs integrateincreasing amounts of functionality, it is vital thatdesigners have access to proven, up-to-date IP fromreliable sources.
上传时间： 2013-11-15
上传用户：lyy1234
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
