All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
Abstract: This application note explains the hardware of different types of 1-Wire® interfaces and software examples adapted to this hardware with a focus on serial ports. Depending on the types of iButtons required for a project and the type of computer to be used, the most economical interface is easily found. The hardware examples shown are basically two different types: 5V general interface and 12V RS-232 interface. Within the 5V group a common printed circuit board could be used for all circuits described. The variations can be achieved by different populations of components. The same principal is used for the 12V RS-232 interface. The population determines if it is a Read all or a Read/Write all type of interface. There are other possible circuit implementations to create a 1-Wire interface. The circuits described in this application note cover many different configurations. For a custom application, one of the described options can be adapted to meet individual needs.
标签： iButtons Reading Writing and
上传时间： 2013-10-29
上传用户：long14578
The 87LPC76X Microcontroller combines in a small package thebenefits of a high-performance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An overview of the I2C bus and description of the bussupport hardware in the 87LPC76X microcontrollers appears inapplication note AN464, Using the 87LPC76X Microcontroller as anI2C Bus Master. That application note includes a programmingexample, demonstrating a bus-master code. Here we show anexample of programming the microcontroller as an I2C slave.The code listing demonstrates communications routines for the87LPC76X as a slave on the I2C bus. It compliments the program inAN464 which demonstrates the 87LPC76X as an I2C bus master.One may demonstrate two 87LPC76X devices communicating witheach other on the I2C bus, using the AN464 code in one, and theprogram presented here in the other. The examples presented hereand in AN464 allow the 87LPC76X to be either a master or a slave,but not both. Switching between master and slave roles in amultimaster environment is described in application note AN435.The software for a slave on the bus is relatively simple, as theprocessor plays a relatively passive role. It does not initiate bustransfers on its own, but responds to a master initiating thecommunications. This is true whether the slave receives or transmitsdata—transmission takes place only as a response to a busmaster’s request. The slave does not have to worry about arbitrationor about devices which do not acknowledge their address. As theslave is not supposed to take control of the bus, we do not demandit to resolve bus exceptions or “hangups”. If the bus becomesinactive the processor simply withdraws, not interfering with themaster (or masters) on the bus which should (hopefully) try toresolve the situation.
上传时间： 2013-11-19
上传用户：shirleyYim
The 87C576 includes two separate methods of programming theEPROM array, the traditional modified Quick-Pulse method, and anew On-Board Programming technique (OBP).Quick Pulse programming is a method using a number of devicepins in parallel (see Figure 1) and is the traditional way in which87C51 family members have been programmed. The Quick-Pulsemethod supports the following programming functions:– program USER EPROM– verify USER EPROM– program KEY EPROM– program security bits– verify security bits– read signature bytesThe Quick-Pulse method is quite easily suited to standardprogramming equipment as evidenced by the numerous vendors of87C51 compatible programmers on the market today. Onedisadvantage is that this method is not well suited to programming inthe embedded application because of the large number of signallines that must be isolated from the application. In addition, parallelsignals from a programmer would need to be cabled to theapplication’s circuit board, or the application circuit board wouldneed to have logic built-in to perform the programming functions.These requirements have generally made in-circuit programmingusing the modified Quick Pulse method impractical in almost all87C51 family applications.
上传时间： 2013-10-21
上传用户：xiaozhiqban
CAN与RS232转换节点的设计与实现 介绍将CAN总线接口与RS232总线接口相互转换的设计方法和2种总线电平转换关系，实现CAN总线与各模块的接口设计，制定了相应的软硬件设计方案，并给出软件设计流程图以及部分硬件设计原理图。为CAN总线与RS232总线互联提供了一种方法，对CAN总线与RS232总线接口设备的互联和广泛应用的实现具有重要意义。关键词：CAN总线；RS-232总线；串行通信Design and Realization of CAN and RS232 Transformation NodeZHOU Wei, CHENG Xiao-hong(Information Institute, Wuhan University of Technology, Wuhan 430070)【Abstract】This paper introduces one design method of the CAN bus interface and the RS232 bus interface interconversion, emphasizes two kindof bus level transformation relations, realizes the CAN bus and various modules connection design, formulates the design proposal of correspondingsoftware and hardware, and gives the flow chart of software design as well as the partial schematic diagram of hardware design. It providesonemethod for the CAN bus and the RS232 bus interconnection, has the vital significance to widespread application realization of the CAN busand theRS232 bus interface equipment interconnection.【Key words】CAN bus; RS-232 bus; serial communication
上传时间： 2013-11-04
上传用户：leesuper
基于ADSP-BF561的数字摄像系统设计Design of Digital Video Camera System Based on Digital Signal ProcessorADSP-BF561（浙江大学 信息与通信工程研究所，浙江 杭州 310027） 马海杰, 刘云海摘要：介绍了基于ADI双核的数字信号处理芯片ADSP-BF561 的数字摄像系统实现方案。系统包括硬件和软件两部分，硬件主要有ADSP-BF561及其外围电路、音视频模数/数模转换、CF卡/微硬盘接口等部分。软件主要有操作系统及音视频编解码算法等部分。关键词：ADSP-BF561 ;数字摄像机;微硬盘;MPEG-4;A/D;D/A中图分类号:TN948.41文献标识码:AAbstract: An implementation of digital video camera system based on ADI dual core digital signal processor ADSP-BF561 is introduced. The system can be divided into two parts——hardware and software design. The hardware design includes ADSP-BF561 and perpheral apparatus, A/D,D/A, CF card or Microdrive and so on. The software includes operating system , audio and video coding algorithm.Key words: ADSP-BF561; digital video camera; microdrive; MPEG-4;A/D;D/A
上传时间： 2013-11-10
上传用户：yl1140vista
微处理器及微型计算机的发展概况 第一代微处理器是以Intel公司1971年推出的4004，4040为代表的四位微处理机。 第二代微处理机（1973年~1977年），典型代表有：Intel 公司的8080、8085；Motorola公司的M6800以及Zlog公司的Z80。 第三代微处理机 第三代微机是以16位机为代表，基本上是在第二代微机的基础上发展起来的。其中Intel公司的8088。8086是在8085的基础发展起来的；M68000是Motorola公司在M6800 的基础发展起来的； 第四代微处理机 以Intel公司1984年10月推出的80386CPU和1989年4月推出的80486CPU为代表， 第五代微处理机的发展更加迅猛，1993年3月被命名为PENTIUM的微处理机面世，98年PENTIUM 2又被推向市场。 INTEL CPU 发展历史Intel第一块CPU 4004,4位主理器,主频108kHz,运算速度0.06MIPs(Million Instructions Per Second, 每秒百万条指令),集成晶体管2,300个,10微米制造工艺,最大寻址内存640 bytes,生产曰期1971年11月. 8085,8位主理器,主频5M,运算速度0.37MIPs,集成晶体管6,500个,3微米制造工艺,最大寻址内存64KB,生产曰期1976年 8086,16位主理器,主频4.77/8/10MHZ,运算速度0.75MIPs,集成晶体管29,000个,3微米制造工艺,最大寻址内存1MB,生产曰期1978年6月. 80486DX,DX2,DX4,32位主理器,主频25/33/50/66/75/100MHZ,总线频率33/50/66MHZ,运算速度20~60MIPs,集成晶体管1.2M个,1微米制造工艺,168针PGA,最大寻址内存4GB,缓存8/16/32/64KB,生产曰期1989年4月 Celeron一代, 主频266/300MHZ(266/300MHz w/o L2 cache, Covington芯心 (Klamath based),300A/333/366/400/433/466/500/533MHz w/128kB L2 cache, Mendocino核心 (Deschutes-based), 总线频率66MHz,0.25微米制造工艺,生产曰期1998年4月) Pentium 4 (478针),至今分为三种核心:Willamette核心(主频1.5G起,FSB400MHZ,0.18微米制造工艺),Northwood核心(主频1.6G~3.0G,FSB533MHZ,0.13微米制造工艺, 二级缓存512K),Prescott核心(主频2.8G起,FSB800MHZ,0.09微米制造工艺,1M二级缓存,13条全新指令集SSE3),生产曰期2001年7月. 更大的缓存、更高的频率、 超级流水线、分支预测、乱序执行超线程技术 微型计算机组成结构单片机简介单片机即单片机微型计算机，是将计算机主机(CPU、 内存和I/O接口)集成在一小块硅片上的微型机。 三、计算机编程语言的发展概况 机器语言 机器语言就是0，1码语言，是计算机唯一能理解并直接执行的语言。汇编语言 用一些助记符号代替用0，1码描述的某种机器的指令系统，汇编语言就是在此基础上完善起来的。高级语言 BASIC，PASCAL，C语言等等。用高级语言编写的程序称源程序，它们必须通过编译或解释，连接等步骤才能被计算机处理。 面向对象语言 C++，Java等编程语言是面向对象的语言。 1.3 微型计算机中信息的表示及运算基础（一） 十进制ND有十个数码：0～9，逢十进一。 例 1234.5=1×103 +2×102 +3×101 +4×100 +5×10-1加权展开式以10称为基数，各位系数为0～9，10i为权。 一般表达式：ND= dn-1×10n-1+dn-2×10n-2 +…+d0×100 +d-1×10-1+… （二） 二进制NB两个数码：0、1, 逢二进一。 例 1101.101=1×23+1×22+0×21+1×20+1×2-1+1×2-3 加权展开式以2为基数，各位系数为0、1， 2i为权。 一般表达式： NB = bn-1×2n-1 + bn-2×2n-2 +…+b0×20 +b-1×2-1+… （三）十六进制NH十六个数码0～9、A～F，逢十六进一。 例：DFC.8=13×162 +15×161 +12×160 +8×16-1 展开式以十六为基数，各位系数为0～9，A～F，16i为权。 一般表达式： NH= hn-1×16n-1+ hn-2×16n-2+…+ h0×160+ h-1×16-1+… 二、不同进位计数制之间的转换 （二）二进制与十六进制数之间的转换 24=16 ，四位二进制数对应一位十六进制数。举例：（三）十进制数转换成二、十六进制数整数、小数分别转换 1.整数转换法“除基取余”：十进制整数不断除以转换进制基数，直至商为0。每除一次取一个余数，从低位排向高位。举例： 2. 小数转换法“乘基取整”：用转换进制的基数乘以小数部分，直至小数为0或达到转换精度要求的位数。每乘一次取一次整数，从最高位排到最低位。举例： 三、带符号数的表示方法 机器数：机器中数的表示形式。真值： 机器数所代表的实际数值。举例:一个8位机器数与它的真值对应关系如下： 真值： X1=+84=+1010100B X2=-84= -1010100B 机器数：[X1]机= 01010100 [X2]机= 11010100(二)原码、反码、补码最高位为符号位，0表示 “+”，1表示“－”。 数值位与真值数值位相同。 例 8位原码机器数： 真值： x1 = +1010100B x2 =－ 1010100B 机器数： [x1]原 = 01010100 [x2]原 = 11010100原码表示简单直观,但0的表示不唯一，加减运算复杂。 正数的反码与原码表示相同。 负数反码符号位为 1，数值位为原码数值各位取反。 例 8位反码机器数： x= +4： [x]原= 00000100 [x]反= 00000100 x= -4： [x]原= 10000100 [x]反= 111110113、补码（Two’s Complement）正数的补码表示与原码相同。 负数补码等于2n－abs（x）8位机器数表示的真值四、 二进制编码例：求十进制数876的BCD码 876= 1000 0111 0110 BCD 876= 36CH = 1101101100B 2、字符编码 美国标准信息交换码ASCII码，用于计算 机与计算机、计算机与外设之间传递信息。 3、汉字编码 “国家标准信息交换用汉字编码”（GB2312-80标准），简称国标码。 用两个七位二进制数编码表示一个汉字 例如“巧”字的代码是39H、41H汉字内码例如“巧”字的代码是0B9H、0C1H1·4 运算基础 一、二进制数的运算加法规则：“逢2进1” 减法规则：“借1当2” 乘法规则：“逢0出0，全1出1”二、二—十进制数的加、减运算 BCD数的运算规则 循十进制数的运算规则“逢10进1”。但计算机在进行这种运算时会出现潜在的错误。为了解决BCD数的运算问题，采取调整运算结果的措施：即“加六修正”和“减六修正”例：10001000(BCD)+01101001(BCD) =000101010111(BCD) 1 0 0 0 1 0 0 0 ＋ 0 1 1 0 1 0 0 1 1 1 1 1 0 0 0 1 ＋ 0 1 1 0 0 1 1 0 ……调整 1 0 1 0 1 0 1 1 1 进位 例： 10001000(BCD)－ 01101001(BCD)= 00011001(BCD) 1 0 0 0 1 0 0 0 － 0 1 1 0 1 0 0 1 0 0 0 1 1 1 1 1 － 0 1 1 0 ……调整 0 0 0 1 1 0 0 1 三、 带符号二进制数的运算 1.5 几个重要的数字逻辑电路编码器译码器计数器微机自动工作的条件程序指令顺序存放自动跟踪指令执行1.6 微机基本结构微机结构各部分组成连接方式1、以CPU为中心的双总线结构；2、以内存为中心的双总线结构；3、单总线结构CPU结构管脚特点 1、多功能；2、分时复用内部结构 1、控制; 2、运算; 3、寄存器; 4、地址程序计数器堆栈定义 1、定义；2、管理；3、堆栈形式
上传时间： 2013-10-17
上传用户：erkuizhang
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上传时间： 2013-10-22
上传用户：liu999666
波长信号的解调是实现光纤光栅传感网络的关键，基于现有的光纤光栅传感器解调方法，提出一种基于FPGA的双匹配光纤光栅解调方法，此系统是一种高速率、高精度、低成本的解调系统，并且通过引入双匹配光栅有效地克服了双值问题同时扩大了检测范围。分析了光纤光栅的测温原理并给出了该方案软硬件设计，综合考虑系统的解调精度和FPGA的处理速度给出了基于拉格朗日的曲线拟合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
上传时间： 2014-07-24
上传用户：caiguoqing
