一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含TESTBENCH
标签: using Fifo registers declared
上传时间: 2015-12-15
上传用户:Avoid98
TESTBENCHes have become an integral part of the design process, enabling you to verify that your HDL model is sufficiently tested before implementing your design and helping you automate the design verification process. It is essential, therefore, that you have confidence your TESTBENCH is thoroughly exercising your design. Collecting code coverage statistics during simulation helps to ensure the quality and thoroughness of your tests.
标签: TESTBENCHes enabling integral process
上传时间: 2014-01-25
上传用户:ynzfm
一个同步FIFO,包括TESTBENCH,
标签: FIFO
上传时间: 2014-01-01
上传用户:cx111111
I2C controller的源码,包括TESTBENCH在内,里面包含有EEPROM的behaving model,前些日子在本站下了一个EEPROM的behaving model,发现可能只是作者的初版,里面错误比较多,因此上传一个能编译拿过来就能用的环境。
标签: controller I2C 源码
上传时间: 2015-12-23
上传用户:ryb
booth乘法器电路,基四实现,附带有TESTBENCH
上传时间: 2013-12-23
上传用户:talenthn
TESTBENCHes have become an integral part of the design process, enabling you to verify that your HDL model is sufficiently tested before implementing your design and helping you automate the design verification process. It is essential, therefore, that you have confidence your TESTBENCH is thoroughly exercising your design. Collecting code coverage statistics during simulation helps to ensure the quality and thoroughness of your tests.
标签: TESTBENCHes enabling integral process
上传时间: 2016-03-24
上传用户:1109003457
i2c总线控制器ipcore,包含TESTBENCH
上传时间: 2013-12-25
上传用户:change0329
此代码实现不同图像颜色制式之间的相互转换,如XYZ<->RGB, 不同标准的RGB<->RGB 以及RGB<->YCbCr之间的转换,包内含有matlab仿真代码m文件、VHDL代码.v文件以及modelsim仿真的TESTBENCH文件,相信对大家有一定的帮助
上传时间: 2016-05-26
上传用户:klin3139
spi bootloader详细资料,里面包含C代码和VHDL代码以及TESTBENCH以及相关的说明文档,有兴趣的朋友可以下来看看。
标签: bootloader spi
上传时间: 2014-01-06
上传用户:talenthn
一个桶形移位寄存器的.v文件,含TESTBENCH
标签: 移位寄存器
上传时间: 2014-12-04
上传用户:lingzhichao