The MC68HC05K0 is a low cost, low pin countsingle chip microcomputer with 504 bytes of userROM and 32 bytes of RAM. The MC68HC05K0 isa member of the 68HC05K series of devices whichare available in 16-pin DIL or SOIC packages.It uses the same CPU as the other devices in the68HC05 family and has the same instructions andregisters. Additionally, the device has a 15-stagemulti-function timer and 10 general purposebi-directional I/0 lines. A mask option is availablefor software programmable pull-downs on all ofthe I/O pins and four of the pins are capable ofgenerating interrupts.The device is ideally suited for remote-controlkeyboard applications because the pull-downs andthe interrupt drivers on the port pins allowkeyboards to be built without any externalcomponents except the keys themselves. There isno need for external pull-up or pull-down resistors,or diodes for wired-OR interrupts, as these featuresare already designed into the device.
上传时间： 2014-01-24
上传用户：zl5712176
基于单片机的汽车多功能报警系统设计The Design of Automobile Multi-function AlarmingBased on Single Chip Computer刘法治赵明富宁睡达(河 南 科 技 学 院 ，新 乡 453 00 3)摘要介绍了一种基于单片机控制的汽车多功能报警系统，它能对汽车的润滑系统油压、制动系统气压、冷却系统温度、轮胎欠压及防盗进行自动检测，并在发现异常情况时，发出声光报警。阐述了该报警系统的硬件组成及软件设计方法。关键词单片机传感器数模转换报警Abstract Am ulti-fimctiona utomobilea larnungs ystemb asedo ns inglec hipc omputerco ntorlis in torducedin th isp aper.Th eo ilpr essuero flu bricatesystem, air pressure of braking system, temperature of cooling system, under pressure of tyre and guard against theft， detected automaticaly场thesystem. Audio and visual alarms wil be provided under abnormal conditions厂The hardware composition and software design of the system， described.Keywords Singlec hipc omputer Sensor Digital-t-oanaloguec onversion Alarmin 汽车多功能报苦器硬件系统设计根据 系 统 实际需要和产品性价比，选用ATMEL公司新生产的采用CMOs工艺的低功耗、高性能8位单片机AT89S52作为系统的控制器。AT89S52的片内有8k Bytes LSP Flash闪烁存储器，可进行100(〕次写、擦除操作;256Bytes内部数据存储器(RAM);3 2 根可编程输N输出线;2个可编程全双工串行通道;看门狗(WTD)电路等。系统由传感器、单片机、模数转换器、无线信号发射电路、指示灯驱动电路、声光报警驱动电KD一9563，发出三声二闪光。并触发一个高电平，驱动无线信号发射电路。
上传时间： 2013-11-09
上传用户：gxmm
基于USB接口的数据采集模块的设计与实现Design and Implementation of USB-Based Data Acquisition Module路 永 伸(天津科技大学电子信息与自动化学院，天津300222)摘要文中给出基于USB接口的数据采集模块的设计与实现。硬件设计采用以Adpc831与PDIUSBDI2为主的器件进行硬件设计，采用Windriver开发USB驱动，并用Visual C十十6.0对主机软件中硬件接口操作部分进行动态链接库封装。关键词USB 数据采集Adpc831 PDNSBDI2 Windriver动态链接库Abstract T hed esigna ndim plementaitono fU SB-BasedD ataA cquisiitonM oduleis g iven.Th ec hips oluitonm ainlyw ithA dpc831a ndP DTUSBD12i sused for hardware design. The USB drive is developed场Wmdriver, and the operation on the hardware interface is packaged into Dynamic Link Libraries场Visual C++6.0. Keywords USB DataA cquisition Adttc831 PDfUSBD12 Windriver0 引言US B总 线 是新一代接口总线，最初推出的目的是为了统一取代PC机的各类外设接口，迄今经历了1.0,1.1与2.0版本3个标准。在国内基于USB总线的相关设计与开发也得到了快速的发展，很多设计者从各自的应用领域，用不同方案设计出了相应的装置[1,2]。数据采集是工业控制中一个普遍而重要的环节，因此开发基于USB接口的数据采集模块具有很强的现实应用意义。虽然 US B总线标准已经发展到2.0版本，但由于工业控制现场干扰信号的情况比较复杂，高速数据传输的可靠性不容易被保证，并且很多场合对数据采集的实时性要求并不高，开发2.0标准产品的成本又较1.1标准产品高，所以笔者认为，在工业控制领域，目前开发基于USB总线1.1标准实现的数据采集模块的实用意义大于相应2.0标准模块。
上传时间： 2013-10-23
上传用户：q3290766
一种基于ST62单片机的称重显示控制器A Weighing Display Controller Based on ST62 Single Chip Computer祛 FA(上海时博飞奥控制系统有限公司，上海201100)摘要在介绍了基于ST62单片机的基础上，详细描述了称重显控制器的硬件设计和软件设计思路。该控制器结构简单、操作方便、抗扰能力强等优点;具有较好的推广应用价值。关键词称重显示控制仪ST62单片机硬件设计软件设计Abstract Ont heb asiso fin torductiono fST 62s inglec hipc omputer,th ed esignc oncrptof h ardwarea nds oftwarefo rw eighingd isplayc ontorleris d escrbed.The controler features simple structure, ease operation, powerful capability of anti-interference, etc.，it is wealth to be promoted into practicalapplicationsKeywords We妙吨display0 引言ST62s inglec hip Hardwared esign Softwaer design备 份 振 荡器，振荡器保护电路，上电复位及低压检测复称 重 显 示控制器是一种具有数字显示、开关量输出、定值控制和通信功能的以微机为操作核心的称重控制装置。它是电子衡器的重要基础部件，直接影响电子衡器及电子称重系统的功能和性能。与合适的传感器及承重传力复位系统组合可组成配料秤、料斗秤、定值秤、平台秤、汽车秤等，广泛应用于电力、化工、建筑、冶金、交通运输、食品、军工等部门，是进行自动称重配料控制和生产过程自动化必不可少的重要检测、控制装置。随着 称 重 计量自动化水平的提高，对称重显示控制器的要求也越来越高。为实现低漂移、高稳定，本控制器采用低漂移、高增益放大器AD620和高分辨率的A/D转换器CS5550。为提高稳定性和可靠性，采用集成度高的、抗干扰能力强的ST62单片机。
上传时间： 2013-10-29
上传用户：钓鳌牧马
单片机系统“PC”失控的软件措施Software Measure of GettingO uto fC ontrolfo r“PC"in S ingleC hipC omputerS ystem谧 加 春 王 晓 基 雷 小 华(江 西 理 工 大 学机 电 工 程 学 院 ，赣 州 34 10 00)摘要单片机系统在实际工业现场中可能遇到各种干扰和自身的随机性故障。现场恶劣的环境有可能使计算机系统发生异常，计算机程序指针“PC”失控就是常见的故障之一，如果发生“PC”失控，将导致CPI工作混乱，酿成严重的事故。研究了“PC”失控的原因，并指出软件抗干扰的几种方法，有效保证单片机系统的正常工作。关键词单片机“PC”失控抗干扰Abstract Inp racticalin dustrialfi elds,th ereis v ariousin terferencea fectingo perationo fsi nglec hipc omputersy stemsa ndt hec omputersy stems。fac吨random faults饰themselves. It is very common that the severe environment makes the computer systems abnormal. The program counter "PC"gettingo utof co ntorlis on eo fth ec ommonfa ults.If th isoc curs,C PUw ouldb eru nningo utof or deran din torducesse riousan cient.T hec ausesof " PC"geting out of control， studied in this paper and some countermeasures of anti-interference师software are given to ensure single chip computer systemworking properly.Keywords Single。饰computer Porgramc ounter"P C" Anti-interfeernc 在设 计 和 开发单片机系统时，一般难以周全地预计单片机系统在实际工业现场中可能遇到的各种干扰和自身的随机性故障。因此，除了采取防止和抑制干扰的各项措施外，还应该借助于软件措施克服某些干扰，系统还应具备迅速自行恢复的能力。本文介绍的应对单片机系统PC失控的软件措施，设计灵活，节省硬件资源，能保证测控系统长期可靠地运行。MC S- 5 1单片机以其优良的性能价格比大量应用于工业现场测试和控制领域。但是，现场恶劣的环境有可能使计算机系统发生异常，计算机程序指针PC失控就是常见的故障之一，一旦发生PC“走飞”，计算机系统就会出现工作混乱，酿成严重的事故。为 了 在 CP 失控时尽量减少由此带来的不利影响，并尽快使系统恢复正常，需要采取一定的软件措施和硬件措施。常见的硬件措施有“看门狗”电路。软件措施设置的前提条件是:①在干扰作用下，微机系统硬件部分不会受到任何损坏，或者损坏部分设置有监测状态可供查询;②程序区不会受到干扰侵害。单片机系统的程序和表格以及重要的参数均设置在ROM区，不会因干扰的侵人而改变;③ RAM区中的重要数据不会被破坏，或者虽然被破坏，但是可以重新建立。
上传时间： 2013-11-02
上传用户：bhqrd30
自动检测80C51 串行通讯中的波特率本文介绍一种在80C51 串行通讯应用中自动检测波特率的方法。按照经验，程序起动后所接收到的第1 个字符用于测量波特率。这种方法可以不用设定难于记忆的开关，还可以免去在有关应用中使用多种不同波特率的烦恼。人们可以设想：一种可靠地实现自动波特检测的方法是可能的，它无须严格限制可被确认的字符。问题是：在各种的条件下，如何可以在大量允许出现的字符中找出波特率的定时间隔。显然，最快捷的方法是检测一个单独位时间（single bit time），以确定接收波特率应该是多少。可是，在RS-232 模式下，许多ASCII 字符并不能测量出一个单独位时间。对于大多数字符来说，只要波特率存在合理波动（这里的波特率是指标准波特率），从起始位到最后一位“可见”位的数据传输周期就会在一定范围内发生变化。此外，许多系统采用8 位数据、无奇偶校验的格式传输ASCII 字符。在这种格式里，普通ASCII 字节不会有MSB 设定
上传时间： 2013-10-15
上传用户：shirleyYim
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
标签： Base-Station Applications Single-Chip Transceiver
上传时间： 2013-11-07
上传用户：songrui
The SDI standards are the predominant standards for uncompressed digital videointerfaces in the broadcast studio and video production center. The first SDI standard,SD-SDI, allowed standard-definition digital video to be transported over the coaxial cableinfrastructure initially installed in studios to carry analog video. Next, HD-SDI wasto support high-definition video. Finally, dual link HD-SDI and 3G-SDIdoubled the bandwidth of HD-SDI to support 1080p (50 Hz and 60 Hz) and other videoformats requiring more bandwidth than HD-SDI provides.
上传时间： 2013-10-08
上传用户：yjj631
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
上传时间： 2013-11-01
上传用户：dingdingcandy
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
