All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS SERIES: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
The MC68HC05K0 is a low cost, low pin countsingle chip microcomputer with 504 bytes of userROM and 32 bytes of RAM. The MC68HC05K0 isa member of the 68HC05K SERIES of devices whichare available in 16-pin DIL or SOIC packages.It uses the same CPU as the other devices in the68HC05 family and has the same instructions andregisters. Additionally, the device has a 15-stagemulti-function timer and 10 general purposebi-directional I/0 lines. A mask option is availablefor software programmable pull-downs on all ofthe I/O pins and four of the pins are capable ofgenerating interrupts.The device is ideally suited for remote-controlkeyboard applications because the pull-downs andthe interrupt drivers on the port pins allowkeyboards to be built without any externalcomponents except the keys themselves. There isno need for external pull-up or pull-down resistors,or diodes for wired-OR interrupts, as these featuresare already designed into the device.
上传时间： 2014-01-24
上传用户：zl5712176
The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) processor caches and/or other data into the FPGA after the FPGAhas been configured, thus achieving partial reconfiguration. The USR_ACCESS_VIRTEX4register is programmed through the bitstream with a command that writes a SERIES of 32-bitwords.
标签： USR_ACCESS PowerPC XAPP 719
上传时间： 2013-11-13
上传用户：我累个乖乖
XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接 The I/Os in Xilinx® 7 SERIES FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 SERIES HP I/O banks with 2.5V and 3.3V systems
上传时间： 2013-11-19
上传用户：yyyyyyyyyy
本文主要通过介绍PLC通讯的意义和三菱FX系列PLC的四种通讯方式，并重点介绍FX系列PLC与计算机无协议通讯，主要从无协议通讯的硬件、配线、数据寄存器设置、PLC与计算机无协议通讯的指令用法、PLC程序编写和计算机VB程序的编写来说明无协议通讯的过程和一般方法。 My dissertation introduces the significance of PLC communications and the four means of communication of Mitsubishi FX’s PLC, And highlights the no protocol communications of FX SERIES PLC and computer, no protocol communications hardware, wiring, Register data set, and the usage of command about no protocol communications, How to write PLC program and computer VB program to illustrate the process of no protocol communications and general method.
上传时间： 2014-11-29
上传用户：Jerry_Chow
ARM is the world’s leading semiconductor IP company with 22 Million processors entering the market each day.
标签： Development_FSL Embedded Kinetis SERIES
上传时间： 2013-11-01
上传用户：kaixinxin196
The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) processor caches and/or other data into the FPGA after the FPGAhas been configured, thus achieving partial reconfiguration. The USR_ACCESS_VIRTEX4register is programmed through the bitstream with a command that writes a SERIES of 32-bitwords.
标签： USR_ACCESS PowerPC XAPP 719
上传时间： 2013-12-23
上传用户：yuanwenjiao
XAPP520将符合2.5V和3.3V I/O标准的7系列FPGA高性能I/O Bank进行连接 The I/Os in Xilinx® 7 SERIES FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 SERIES HP I/O banks with 2.5V and 3.3V systems
上传时间： 2013-11-06
上传用户：wentianyou
Abstract: Many modern industrial, medical, and commercial applications require temperature measurements in the extended temperature rangewith accuracies of ±0.3°C or better, performed with reasonable cost and often with low power consumption. This article explains how platinumresistance temperature detectors (PRTDs) can perform measurements over wide temperature ranges of -200°C to +850°C, with absolute accuracyand repeatability better than ±0.3°C, when used with modern processors capable of resolving nonlinear mathematical equation quickly and costeffectively. This article is the second installment of a SERIES on PRTDs. For the first installment, please read application note 4875, "High-Accuracy Temperature Measurements Call for Platinum Resistance Temperature Detectors (PRTDs) and Precision Delta-Sigma ADCs."
上传时间： 2013-11-06
上传用户：WMC_geophy
Automobiles, aircraft, marine vehicles, uninterruptiblepower supplies and telecom hardware represent areasutilizing SERIES connected battery stacks. These stacksof individual cells may contain many units, reaching potentialsof hundreds of volts. In such systems it is oftendesirable to accurately determine each individual cell’svoltage. Obtaining this information in the presence of thehigh “common mode” voltage generated by the batterystack is more diffi cult than might be supposed.
上传时间： 2013-10-24
上传用户：kang1923
