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SECOND-Clock

  • JOECELKO’S SQL PUZZLES & ANSWERS Second Edition

    JOECELKO’S SQL PUZZLES & ANSWERS Second Edition

    标签: JOECELKO ANSWERS Edition PUZZLES

    上传时间: 2017-09-20

    上传用户:lingzhichao

  • Clock based on the VHDL design language, the revised time alarm can be set up

    Clock based on the VHDL design language, the revised time alarm can be set up

    标签: the language revised design

    上传时间: 2013-12-09

    上传用户:haoxiyizhong

  • Inverted pendulum in cart controled by torque. It contains regulators: one to move it, second to sta

    Inverted pendulum in cart controled by torque. It contains regulators: one to move it, second to stabilize pendulum, and last to stabilize the cart

    标签: regulators controled Inverted pendulum

    上传时间: 2017-09-24

    上传用户:

  • 8051 clock very good for using

    8051 clock very good for using

    标签: clock using 8051 very

    上传时间: 2014-01-26

    上传用户:lepoke

  • 8051 clock very good for using

    8051 clock very good for using

    标签: clock using 8051 very

    上传时间: 2013-12-13

    上传用户:大三三

  • this source code for displayed clock & alarm in 2*16 LCD and writed in codevisionAVR for useable AVR

    this source code for displayed clock & alarm in 2*16 LCD and writed in codevisionAVR for useable AVR mcu

    标签: codevisionAVR for displayed useable

    上传时间: 2017-09-26

    上传用户:wpt

  • Bayesian Artificial Intelligence (Second Edition)

    Bayesian Artificial Intelligence (Second Edition)  English Edition, 2011 Authors: Kevin B. Korb, Ann E. Nicholson

    标签: Intelligence Artificial Bayesian Edition Second

    上传时间: 2018-01-25

    上传用户:zhkunhua

  • 时钟芯片RX8025T

    RX-8801 SA Features built-in 32.768 kHz DTCXO, High Stability Supports l'C-Bus's high speed mode (400 kHz)Alarm interrupt function for day, date, hour, and minute settings Fixed-cycle timer interrupt function Time update interrupt function32.768 kHz output with OE function Auto correction of leap years Wide interface voltage range: 2.2 V to 5.5 V Wide time-keeping voltage range:1.8 V to 5.5 V Low current consumption: 0.84A/3V (Typ.)is an IC bus interface-compliant real-time clock which includes a 32.768 kHz DTCXO In addition to providing a calendar (year, month, date, day, hour, minute, second) function and a clock counter function, this module provides an abundance of other functions including an alarm function, fixed-cycle timer unction, time update interrupt function, and 32.768 kHz output function.The devices in this module are fabricated via a C-MOS process for low current consumption, which enables ong-term battery back-up.

    标签: 时钟芯片 rx8025t

    上传时间: 2022-06-17

    上传用户:

  • 嵌入式实时操作系统MicroCOS_II光盘内容.rar

    MicroC/OS-II The Real-Time Kernel Second Edition By Jean J. Labrosse CMP Books, CMP Media LLC Copyright 2002 by CMP Books ISBN 1-57820-103-9 CMP Books CMP Media LLC 1601 West 23rd Street, Suite 200 Lawrence, Kansas 66046 785-841-1631 www.cmpbooks.com email: books@cmp.com The programs and applications on this disk have been carefully tested, but are not guaranteed for any particular purpose. The publisher does not offer any warranties and does not guarantee the accuracy, adequacy, or completeness of any information and is not responsible for any errors or omissions or the results obtained from use of such information.

    标签: MicroCOS_II 嵌入式 实时操作系统

    上传时间: 2013-06-09

    上传用户:zhyiroy

  • 软件无线电中数字下变频技术研究及FPGA实现.rar

    软件无线电(SDR,Software Defined Radio)由于具备传统无线电技术无可比拟的优越性,已成为业界公认的现代无线电通信技术的发展方向。理想的软件无线电系统强调体系结构的开放性和可编程性,减少灵活性著的硬件电路,把数字化处理(ADC和DAC)尽可能靠近天线,通过软件的更新改变硬件的配置、结构和功能。目前,直接对射频(RF)进行采样的技术尚未实现普及的产品化,而用数字变频器在中频进行数字化是普遍采用的方法,其主要思想是,数字混频器用离散化的单频本振信号与输入采样信号在乘法器中相乘,再经插值或抽取滤波,其结果是,输入信号频谱搬移到所需频带,数据速率也相应改变,以供后续模块做进一步处理。数字变频器在发射设备和接收设备中分别称为数字上变频器(DUC,Digital Upper Converter)和数字下变频器(DDC,Digital Down Converter),它们是软件无线电通信设备的关键部什。大规模可编程逻辑器件的应用为现代通信系统的设计带来极大的灵活性。基于FPGA的数字变频器设计是深受广大设计人员欢迎的设计手段。本文的重点研究是数字下变频器(DDC),然而将它与数字上变频器(DUC)完全割裂后进行研究显然是不妥的,因此,本文对数字上变频器也作适当介绍。 第一章简要阐述了软件无线电及数字下变频的基本概念,介绍了研究背景及所完成的主要研究工作。 第二章介绍了数控振荡器(NCO),介绍了两种实现方法,即基于查找表和基于CORDIC算法的实现。对CORDIc算法作了重点介绍,给出了传统算法和改进算法,并对基于传统CORDIC算法的NCO的FPGA实现进行了EDA仿真。 第三章介绍了变速率采样技术,重点介绍了软件无线电中广泛采用的级联积分梳状滤波器 (cascaded integratot comb, CIC)和ISOP(Interpolated Second Order Polynomial)补偿法,对前者进行了基于Matlab的理论仿真和FPGA实现的EDA仿真,后者只进行了基于Matlab的理论仿真。 第四章介绍了分布式算法和软件无线电中广泛采用的半带(half-band,HB)滤波器,对基于分布式算法的半带滤波器的FPGA实现进行了EDA仿真,最后简要介绍了FIR的多相结构。 第五章对数字下变频器系统进行了噪声综合分析,给出了一个噪声模型。 第六章介绍了数字下变频器在短波电台中频数字化应用中的一个实例,给出了测试结果,重点介绍了下变频器的:FPGA实现,其对应的VHDL程序收录在本文最后的附录中,希望对从事该领域设计的技术人员具有一定参考价值。

    标签: FPGA 软件无线电 数字下变频

    上传时间: 2013-06-30

    上传用户:huannan88