Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio ReferenCE designs such as RD2550. For more information on the RD2550, see ReferenCE design 5364, "FemtocellRadio ReferenCE Designs Using the MAX2550–MAX2553 Transceivers."
标签： Base-Station Applications Single-Chip Transceiver
上传时间： 2013-11-05
上传用户：超凡大师
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The ReferenCE design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
上传时间： 2013-10-09
上传用户：guojin_0704
This application note contains a ReferenCE design consisting of HDL IP and Xilinx AdvancedConfiguration Environment (ACE) software utilities that give designers great flexibility increating in-system programming (ISP) solutions. In-system programming support allowsdesigners to revise existing designs, package the new bitstream programming files with theprovided software utilities, and update the remote system through the JTAG interface using theEmbedded JTAG ACE Player.
上传时间： 2013-10-22
上传用户：gai928943
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This ReferenCE system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2014-11-26
上传用户：erkuizhang
The PPC405 Virtex-4 is a wrapper around the Virtex-4PowerPC™ 405 Processor Block primitive. For detailsregarding the PowerPC 405, see the PowerPC 405 ProcessorBlock ReferenCE Guide.
上传时间： 2015-01-02
上传用户：JIUSHICHEN
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The ReferenCE system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control ReferenCE designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
上传时间： 2013-10-28
上传用户：wujijunshi
西门子建筑电器-电气安装技术部发行的各类产品样本：小型断路器、剩余电流保护断路器和模数化产品(中/ 英文)Miniature Circuit-Breakers, Residual Current Operated Circuit-Breakers and Modular Devices (Chinese/English)低压熔断器系统(中/ 英文)Fuse System (Chinese/English)雷击，过电压－不再是问题(中文)Thunderstorms - no problem (Chinese)西门子建筑电器目录(中文)Electrical Installation Technology Catalog (Chinese)终端配电保护产品(中文)5 IN 1 (Chinese)SIKUS 和 STAB UNIVERSAL 目录(中文)SIKUS and STAB UNIVERSAL Catalogue (Chinese)SIKUS HC 目录(中文)SIKUS HC Catalogue (Chinese)SentronTM 母线槽 (中文)SentronTM Busway System (Chinese)SentronTM 母线槽系统快速选型 (准备中) (中文)SentronTM Busway System quick selection (in preparing) (Chinese)建筑低压配电一体化解决方案－住宅小区应用(中文)Building LV PD Solution (Chinese)西门子 DELTA vista“远景”系列开关和插座价目表(中文)Delta vista Switch and Socket Pricelist (Chinese)instabus EIB 面向未来的楼宇智能控制系统(中文)instabus EIB (Chinese)instabus EIB 面向未来的楼宇智能控制系统技术手册 (准备中) (中文)instabus EIB technical handbook (in preparing) (Chinese)西门子电气安装技术业绩卓越(中/ 英文)ET ReferenCE Manual (Chinese/English)
上传时间： 2013-11-23
上传用户：瓦力瓦力hong
The data plane of the ReferenCE design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the ReferenCE clock frequency and the internal PMAdivider settings. The ReferenCE design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上传时间： 2013-12-25
上传用户：jkhjkh1982
Frequently, voltage ReferenCE stability and noise defi nemeasurement limits in instrumentation systems. In particular,ReferenCE noise often sets stable resolution limits.ReferenCE voltages have decreased with the continuingdrop in system power supply voltages, making ReferenCEnoise increasingly important. The compressed signalprocessing range mandates a commensurate reductionin ReferenCE noise to maintain resolution. Noise ultimatelytranslates into quantization uncertainty in A to D converters,introducing jitter in applications such as scales, inertialnavigation systems, infrared thermography, DVMs andmedical imaging apparatus. A new low voltage ReferenCE,the LTC6655, has only 0.3ppm (775nV) noise at 2.5VOUT.Figure 1 lists salient specifi cations in tabular form. Accuracyand temperature coeffi cient are characteristic ofhigh grade, low voltage ReferenCEs. 0.1Hz to 10Hz noise,particularly noteworthy, is unequalled by any low voltageelectronic ReferenCE.
上传时间： 2013-10-30
上传用户：wxhwjf
