为了改变目前电网现场作业管理的变电巡检、变电检修试验、输电线路巡检检修等管理系统各自独立运行，信息不能共享，功能、效率受限，建设和维护成本高的现状，提出了采用B/S+C/S构架模式，将各现场作业管理模块和生产MIS（管理系统）集成为一体的现场作业管理系统的设计方案，做到各子系统和生产MIS软硬资源共享，做到同一数据唯一入口、一处录入多处使用。各子系统设备人员等基础信息来源于生产管理系统，各子系统又是生产管理系统的作业数据、缺陷信息的重要来源。经过研究试用成功和推广应用，目前该系统已在江西电网220 kV及以上变电站全面应用。 Abstract: In order to improve the status that the substation field inspection system， substation equipments maintenance and testing system， power-line inspection and maintenance system are running independent with each other. They can?蒺t share the resource information which accordingly constrains their functions and efficiency， and their construction and maintenance costs are high. This paper introduces a field standardized work management system based on B/S+C/S mode， integrating all field work management systems based on MIS and share the equipments and employee?蒺s data of MIS，the field work data of the sub systems are the source information of MIS， by which the same single data resouce with one-time input can be utilized in multiple places. After the research and testing， this system is triumphantly using in all 220kV and above substations in Jiangxi grid.
上传时间： 2013-11-15
上传用户：han_zh
The PAM2862 is a continuous mode inductivestep-down converter, designed for driving singleor multiple series connected LEDs efficientlyfrom a voltage source higher than the LEDvoltage. The device operates from an inputupply between 6V and 30V and provides anexternally adjustable output current of up to 1A.Depending upon supply voltage and externalcomponents, this can provide up to 24 watts ofoutput power.
上传时间： 2013-11-16
上传用户：司令部正军级
The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
标签： 4channel multiple 9544A 9544
上传时间： 2014-12-28
上传用户：潜水的三贡
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
多远程二极管温度传感器-Design Considerations for pc thermal management Multiple RDTS (remote diode temperature sensing) provides the most accurate method of sensing an IC’s junction temperature. It overcomes thermal gradient and placement issues encountered when trying to place external sensors. PCB component count decreases when using a device that provides multiple inputs.Better temperature sensing improves product performance and reliability. Disk drive data integrity suffers at elevated temperatures. IBM published an article stating that a 5°C rise in operating temperature causes a 15% increase in the drive’s failure rate. The overall performance of a system can be improved by providing a more accurate temperature measurement of the most critical devices allowing them to run just a few degrees hotter.The LM83 directly senses its own temperature and the temperature of three external PN junctions. One is dedicated to the CPU of choice, the other two go to other parts of your system that need thermal monitoring such as the disk drive or graphics chip. The SMBus-compatible LM83 supports SMBus timeout and logic levels. The LM83 has two interrupt outputs; one for user-programmable limits and WATCHDOG capability (INT), the other is a Critical Temperature Alarm output (T_CRIT_A) for system power supply shutdown.
标签： Considerat Design 远程 二极管
上传时间： 2014-12-21
上传用户：ljd123456
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
在Multisim 10软件环境下，设计一种由运算放大器构成的精确可控矩形波信号发生器，结合系统电路原理图重点阐述了各参数指标的实现与测试方法。通过改变RC电路的电容充、放电路径和时间常数实现了占空比和频率的调节，通过多路开关投入不同数值的电容实现了频段的调节，通过电压取样和同相放大电路实现了输出电压幅值的调节并提高了电路的带负载能力，可作为频率和幅值可调的方波信号发生器。Multisim 10仿真分析及应用电路测试结果表明，电路性能指标达到了设计要求。 Abstract: Based on Multisim 10， this paper designed a kind of rectangular-wave signal generator which could be controlled exactly composed of operational amplifier， the key point was how to implement and test the parameter indicators based on the circuit diagram. The duty and the frequency were adjusted by changing the time constant and the way of charging and discharging of the capacitor， the width of frequency was adjusted by using different capacitors provided with multiple switch， the amplitude of output voltage was adjusted by sampling voltage and using in-phase amplifier circuit，the ability of driving loads was raised， the circuit can be used as squarewave signal generator whose frequency and amplitude can be adjusted. The final simulation results of Multisim 10 and the tests of applicable circuit show that the performance indicators of the circuit meets the design requirements.
上传时间： 2014-01-21
上传用户：shen007yue
生成BCD码。 Name: BIN3toBCD4 Func:2字节二进制整数--->>BCD码四字节转换(Comped BCD) Input: 3进制数人低字节到高字节存放在内部RAM50H，51H,52h单元中 Output: BCD码人低位到高位分别存放在内部RAM53H,54H，55H，56H单元中 USE: R7-R0, 56H-50H
标签： BCD BIN3toBCD4 Comped Input
上传时间： 2015-02-02
上传用户：FreeSky
对c语言的简单语法分析器 文件说明： input.txt内为输入的源程序，包括for，while和if else控制等 output.txt内为输出的二元单词序列 k.txt为关键字表 l.txt为运算符和界符表 i.txt为该输入的源程序的标志符 c.txt为常数表 个别表需要序列号，这时各表的序列号默认为从1开始，每行加1。 使用说明： 在提示符下输入input.txt文件的路径和文件名字， 运行完成后，打开文件output.txt看结果。
上传时间： 2013-12-23
上传用户：pompey
