AT89C2051驱动步进电机的电路和源码:AT89C2051驱动步进电机的电路和源码 程序:stepper.c stepper.hex/* * STEPPER.C * sweeping stepper's rotor cw and cww 400 steps * Copyright (c) 1999 by W.Sirichote */＃i nclude c:\mc5151io.h /* include i/o header file */ ＃i nclude c:\mc5151reg.hregister unsigned char j,flag1,temp; register unsigned int cw_n,ccw_n;unsigned char step[8]={0x80,0xc0,0x40,0x60,0x20,0x30,0x10,0x90} #define n 400/* flag1 mask byte 0x01 run cw() 0x02 run ccw() */main(){ flag1=0; serinit(9600); disable(); /* no need timer interrupt */ cw_n = n; /* initial step number for cw */ flag1 |=0x01; /* initial enable cw() */while(1){ { tick_wait(); /* wait for 10ms elapsed */energize(); /* round-robin execution the following tasks every 10ms */ cw(); ccw(); } }}cw(){ IF((flag1&0x01)!=0) { cw_n--; /* decrement cw step number */ IF (cw_n !=0) j++; /* IF not zero increment index j */ else {flag1&=~0x01; /* disable cw() execution */ ccw_n = n; /* reload step number to ccw counter */ flag1 |=0x02; /* enable cww() execution */ } }
上传时间： 2013-11-21
上传用户：boyaboy
The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices IF the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.
上传时间： 2013-10-09
上传用户：3294322651
The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, IF an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
标签： 4channel multiple 9544A 9544
上传时间： 2014-12-28
上传用户：潜水的三贡
C51基本结构程序设计1． 掌握IF语句来实现选择结构，能利用IF语句编写相应的分枝结构的程序。在嵌套IF语句中，一定要搞清楚else与哪个IF结合的问题。2．掌握switch语句来实现多向分枝选择结构，能利用switch语句编写相应的分枝结构的程序。 3. 掌握循环语句的即初始化、循环体、循环控制及结束四个部分，并能进行循环语句的程序设计。分别掌握for 语句、while语句以及do-while语句的使用语法及方法，能利用这三种循环结构进行循环程序设计，理解这三种语句的异同。4．理解并掌握continue、break语句在循环结构和选择结构中的作用。对于goto语句，理解该语句优缺点。C51语言是结构化编程语言。结构化语言的基本元素是模块，它是程序的一部分．只有一个出口和一个入口．不允许有偶然的中途插入或以模块的其它路径退出。结构化编程语言在没有妥善保护或恢复堆栈和其它相关的寄存器之前，不应随便跳入或跳出一个模块。因此使用这种结构化语言进行编程，当要退出中断时，堆栈不会因为程序使用了任何可以接受的命令而崩溃。 结构化程序由若干模块组成，每个模块中包含着若干个基本结构，而每个基本结构中可以有若干条语句。归纳起来，C51程序有顺序结构、选择结构、循环结构共三种结构。
上传时间： 2013-11-01
上传用户：四只眼
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). IF a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin dIFferent operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
标签： synchronous Emulating serial
上传时间： 2014-01-31
上传用户：z1191176801
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even IF anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specIFication between VIL and VIH with a sufficient rise/fall time, as generally usualand specIFied for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even IF the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specIFic sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected IF twoconsecutive samples show dIFferent levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. IF an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result IF the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result IFthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. IF low is sampled, no transition willbe detected. IF the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. IF the previous sample 2) had alreadydetected a high, there is no change. IF the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even IF anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specIFication between VIL and VIH with a sufficient rise/fall time, as generally usualand specIFied for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even IF the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specIFic sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected IF twoconsecutive samples show dIFferent levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. IF an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
Abstract: This application note explains the hardware of dIFferent types of 1-Wire® interfaces and software examples adapted to this hardware with a focus on serial ports. Depending on the types of iButtons required for a project and the type of computer to be used, the most economical interface is easily found. The hardware examples shown are basically two dIFferent types: 5V general interface and 12V RS-232 interface. Within the 5V group a common printed circuit board could be used for all circuits described. The variations can be achieved by dIFferent populations of components. The same principal is used for the 12V RS-232 interface. The population determines IF it is a Read all or a Read/Write all type of interface. There are other possible circuit implementations to create a 1-Wire interface. The circuits described in this application note cover many dIFferent configurations. For a custom application, one of the described options can be adapted to meet individual needs.
标签： iButtons Reading Writing and
上传时间： 2013-10-29
上传用户：long14578
The 87LPC76X Microcontroller combines in a small package thebenefits of a high-performance microcontroller with on-boardhardware supporting the Inter-Integrated Circuit (I2C) bus interface.The 87LPC76X can be programmed both as an I2C bus master, aslave, or both. An overview of the I2C bus and description of the bussupport hardware in the 87LPC76X microcontrollers appears inapplication note AN464, Using the 87LPC76X Microcontroller as anI2C Bus Master. That application note includes a programmingexample, demonstrating a bus-master code. Here we show anexample of programming the microcontroller as an I2C slave.The code listing demonstrates communications routines for the87LPC76X as a slave on the I2C bus. It compliments the program inAN464 which demonstrates the 87LPC76X as an I2C bus master.One may demonstrate two 87LPC76X devices communicating witheach other on the I2C bus, using the AN464 code in one, and theprogram presented here in the other. The examples presented hereand in AN464 allow the 87LPC76X to be either a master or a slave,but not both. Switching between master and slave roles in amultimaster environment is described in application note AN435.The software for a slave on the bus is relatively simple, as theprocessor plays a relatively passive role. It does not initiate bustransfers on its own, but responds to a master initiating thecommunications. This is true whether the slave receives or transmitsdata—transmission takes place only as a response to a busmaster’s request. The slave does not have to worry about arbitrationor about devices which do not acknowledge their address. As theslave is not supposed to take control of the bus, we do not demandit to resolve bus exceptions or “hangups”. IF the bus becomesinactive the processor simply withdraws, not interfering with themaster (or masters) on the bus which should (hopefully) try toresolve the situation.
上传时间： 2013-11-19
上传用户：shirleyYim
5.1 中断基本概念5.1.1 中断基本概念定义：CPU暂停现行程序，转而处理随机到来的事件，待处理完后再回到被暂停的程序继续执行，这个过程就是中断。中断过程：中断处理的隐操作：程序状态及程序断点地址的进栈及出栈。 中断系统其他功能： 支持多中断源和多种中断源。 支持中断屏蔽处理。 支持中断嵌套处理。 支持中断优先级修改。 支持中断结束方式选择。5.1.2 中断类型1.外部硬件(如键盘、鼠标，串口，并口打印机等）中断属性：硬件、可屏蔽、向量。 中断请求：多个中断请求的排队和判优由中断控制器完成，产生的有无中断请求的信号送到CPU的INTR引脚。 中断类型号：通过数据总线送到CPU中。EFLAGS寄存器的IF位影响CPU对中断请求的响应。处理器在当前指令执行结束的时候启动中断识别INTA总线周期。
标签： 中断技术
上传时间： 2013-11-09
上传用户：黄婷婷思密达
