在汽车发动机起动时，若发动机起动后起动机不能及时断电，将会烧毁起动机或损坏飞轮齿环；若变速器不在空档位置起动，则起动机的瞬间动力将使汽车位移，还可能引起交通事故和人身安全。为此介绍一种利用NXP P89LPC901单片机控制的汽车起动保护控制器，通过检测汽车起动开关、变速箱档位、发动机转速，实现对汽车发动机起动过程检测和保护。起动保护控制器在发动机起动过程中通过采用逐个关闭打开负载系统，解决汽车发动机过程中因起动电流大而对汽车电源的冲击影响,延长了电瓶寿命。 Abstract: When the automotive engine is started, the engine start motor and flywheel gear may be damaged， EVEN traffic accidents and personal safeties may be caused by wrong operation or other factors.In order to ensure the automotive engine can be started normally and safely,it is necessary that the protecting measures and methods are considered in the automotive electrical control system.This paper introduces a kind of the automotive engine starting protect controller based on NXP P89LPC901 MCU.The controller can protect the engine starting process by detecting the starter key switch,transmission stall and engine speed.Through the use of close and open load system,the controller can solve the impact on automotive power because of the high-current load in the process of the automobile engine starting, and extend battery life.
上传时间： 2013-10-15
上传用户：mikesering
The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, EVEN when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.
上传时间： 2013-10-09
上传用户：3294322651
The μPSD32xx family, from ST, consists of Flash programmable system devices with a 8032 MicrocontrollerCore. Of these, the μPSD3234A and μPSD3254A are notable for having a complete implementationof the USB hardware directly on the chip, complying with the Universal Serial Bus Specification, Revision1.1.This application note describes a demonstration program that has been written for the DK3200 hardwaredemonstration kit (incorporating a μPSD3234A device). It gives the user an idea of how simple it is to workwith the device, using the HID class as a ready-made device driver for the USB connection.IN-APPLICATION-PROGRAMMING (IAP) AND IN-SYSTEM-PROGRAMMING (ISP)Since the μPSD contains two independent Flash memory arrays, the Micro Controller Unit (MCU) can executecode from one memory while erasing and programming the other. Product firmware updates in thefield can be reliably performed over any communication channel (such as CAN, Ethernet, UART, J1850)using this unique architecture. For In-Application-Programming (IAP), all code is updated through theMCU. The main advantage for the user is that the firmware can be updated remotely. The target applicationruns and takes care on its own program code and data memory.IAP is not the only method to program the firmware in μPSD devices. They can also be programmed usingIn-System-Programming (ISP). A IEEE1149.1-compliant JTAG interface is included on the μPSD. Withthis, the entire device can be rapidly programmed while soldered to the circuit board (Main Flash memory,Secondary Boot Flash memory, the PLD, and all configuration areas). This requires no MCU participation.The MCU is completely bypassed. So, the μPSD can be programmed or reprogrammed any time, anywhere, EVEN when completely uncommitted.Both methods take place with the device in its normal hardware environment, soldered to a printed circuitboard. The IAP method cannot be used without previous use of ISP, because IAP utilizes a small amountof resident code to receive the service commands, and to perform the desired operations.
标签： Demonstration 3200 USB for
上传时间： 2014-02-27
上传用户：zhangzhenyu
Internal Interrupts are used to respond to asynchronous requests from a certain part of themicrocontroller that needs to be serviced. Each peripheral in the TriCore as well as theBus Control Unit, the Debug Unit, the Peripheral Control Processor (PCP) and the CPUitself can generate an Interrupt Request.So what is an external Interrupt?An external Interrupt is something alike as the internal Interrupt. The difference is that anexternal Interrupt request is caused by an external EVENt. Normally this would be a pulseon Port0 or Port1, but it can be EVEN a signal from the input buffer of the SSC, indicatingthat a service is requested.The User’s Manual does not explain this aspect in detail so this ApNote will explain themost common form of an external Interrupt request. This ApNote will show that there is aneasy way to react on a pulse on Port0 or Port1 and to create with this impulse an InterruptService Request. Later in the second part of the document, you can find hints on how todebounce impulses to enable the use of a simple switch as the input device.Note: You will find additional information on how to setup the Interrupt System in theApNote “First steps through the TriCore Interrupt System” (AP3222xx)1. It would gobeyond the scope of this document to explain this here, but you will find selfexplanatoryexamples later on.
上传时间： 2013-10-27
上传用户：zhangyigenius
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, EVEN if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that EVEN if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture EVENts.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, EVEN if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that EVEN if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture EVENts.
上传时间： 2014-04-02
上传用户：han_zh
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, EVEN in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within EVEN smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
USB接口控制器参考设计,xilinx提供VHDL代码 usb xilinx vhdl ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 2 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without EVEN the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
上传时间： 2013-10-12
上传用户：windgate
We offer a broad line of high performance low dropout (LDO) linear regulators with fasttransient response, excellent line and load regulation, and very wide input voltage rangefrom 0.9V to 100V. Output currents range from 20mA to 10A, with positive, negative andmultiple output versions available. Many devices offer output voltage operation <0.8V andsome feature operation as low as 0V, EVEN with a single supply. Most are stable with ceramicoutput capacitors. LDO regulators can be applied in virtually any application.
上传时间： 2013-11-15
上传用户：努力努力再努力
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, EVEN in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within EVEN smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
