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  • 这个设计是使用Virtex-4实现DDR的控制器的

    这个设计是使用Virtex-4实现DDR的控制器的,设计分为三个主要模块:Front-END FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。

    标签: Virtex DDR 控制器

    上传时间: 2017-05-20

    上传用户:llandlu

  • Playfair Cipher 1.not even the large number of keys in a monoalphabetic cipher provides security 2

    Playfair Cipher 1.not even the large number of keys in a monoalphabetic cipher provides security 2.one approach to improving security was to encrypt multiple letters 3.the Playfair Cipher is an example 4.invented by Charles Wheatstone in 1854,but named after his friEND Baron Playfair Playfair Key Matrix 1.a 5X5 matrix of letters based on a keyword 2.fill in letters of keyword (sans duplicates) 3.fill rest of matrix with other letters Encrypting and Decrypting -plaintext is encrypted two letters at a time 1. if a pair is a repeated letter, insert filler like X’ 2. if both letters fall in the same row, replace each with letter to right (wrapping back to start from END) 3. if both letters fall in the same column, replace each with the letter below it (again wrapping to top from bottom) 4. otherwise each letter is replaced by the letter in the same row and in the column of the other letter of the pair

    标签: monoalphabetic Playfair provides security

    上传时间: 2017-05-25

    上传用户:变形金刚

  • Uma modelagem de um cenario basico para quem esta aprENDENDo a usar open/gl na plataforma C++. Utili

    Uma modelagem de um cenario basico para quem esta aprENDENDo a usar open/gl na plataforma C++. Utilizando comandos basicos como setas direcionais e teclas especiais como home, END, page up e page down voce pode navegar por todo o ambiente 3D com muita facilidade.

    标签: aprENDENDo plataforma modelagem cenario

    上传时间: 2014-12-19

    上传用户:ynwbosss

  • 编译课上做的小程序

    编译课上做的小程序,用四种分析方法分别实现(LL1,算符优先,递归下降,简单词法分析) 完成对正则文法所描述的Pascal语言子集单词符号的词法分析程序。 <标识符>→字母︱ <标识符>字母︱ <标识符>数字 <无符号整数>→数字︱ <无符号整数>数字 <单字符分界符> →+ ︱- ︱* ︱ ︱(︱) <双字符分界符>→<大于>=︱<小于>=︱<小于>>︱<冒号>=︱<斜竖>* <小于>→< <等于>→= <大于>→> <冒号> →: <斜竖> →/ 识别语言的保留字 :begin END if then else for do while and or not

    标签: 编译 程序

    上传时间: 2014-06-29

    上传用户:sjyy1001

  • C++ C 词法分析器

    C++ C 词法分析器,编译原理, 运行时输入文件(input.txt)路径,文件内容为{}BEGIN FOR(I=0 I<10 I=I+1){} END

    标签: 分析器

    上传时间: 2013-12-18

    上传用户:mikesering

  • Emdros is a text database middleware-layer aimed at storage and retrieval of "text plus information

    Emdros is a text database middleware-layer aimed at storage and retrieval of "text plus information about that text." This information could be linguistic analyses or other annotations. Emdros provides an abstraction of text that makes it well suited to storing /syntactic analyses/ of text, but other linguistic information is supported as well. Emdros comes with a query-language, MQL, that enables powerful queries. Emdros acts as a middleware-layer between a client (not provided) and a database back-END. Currently, PostgreSQL, MySQL, and SQLite (2 and 3) are supported, but other back-ENDs can easily be added.

    标签: text middleware-layer information retrieval

    上传时间: 2014-01-02

    上传用户:wfeel

  • In communication systems channel poses an important role. channels can convolve many different kind

    In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random. To handle this, multipath affected channels require Equalizers at receaver END. such equalizer uses different learning Algorithms for identifying channels continuously. This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.

    标签: communication important different channels

    上传时间: 2013-12-08

    上传用户:litianchu

  • The emphasis of this book is on real-time application of Synopsys tools, used to combat various pro

    The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, submicron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-END integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.

    标签: application real-time Synopsys emphasis

    上传时间: 2017-07-05

    上传用户:waitingfy

  • P3.20. Consider an analog signal xa (t) = sin (2πt), 0 ≤t≤ 1. It is sampled at Ts = 0.01, 0.05, and

    P3.20. Consider an analog signal xa (t) = sin (2πt), 0 ≤t≤ 1. It is sampled at Ts = 0.01, 0.05, and 0.1 sec intervals to obtain x(n). b) Reconstruct the analog signal ya (t) from the samples x(n) using the sinc interpolation (use ∆ t = 0.001) and determine the frequency in ya (t) from your plot. (Ignore the END effects.) C) Reconstruct the analog signal ya (t) from the samples x (n) using the cubic spline interpolation and determine the frequency in ya (t) from your plot. (Ignore the END effects.)

    标签: Consider sampled analog signal

    上传时间: 2017-07-12

    上传用户:咔乐坞

  • -- Hamming Decoder -- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder a

    -- Hamming Decoder -- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection. -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee USE ieee.std_logic_1164.ALL ENTITY hamdec IS PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4 dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3 sec, ded, ne : OUT BIT) --diagnostic outputs END hamdec ARCHITECTURE ver1 OF hamdec IS BEGIN

    标签: Hamming produced Decoder decoder

    上传时间: 2017-07-15

    上传用户:520