DDR走线要点。
上传时间： 2013-10-22
上传用户：aysyzxzm
SDRAM与DDR布线指南
上传时间： 2013-11-18
上传用户：1142895891
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2014-11-26
上传用户：erkuizhang
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上传时间： 2013-11-24
上传用户：18707733937
用VHDL编写DDR SDRAM Controller的源代码
标签： Controller SDRAM VHDL DDR
上传时间： 2013-12-19
上传用户：hn891122
iptables 簡介.rar DDR
上传时间： 2015-01-19
上传用户：zukfu
DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M
上传时间： 2014-12-02
上传用户：bcjtao
DDR（双速率）SDRAM控制器参考设计，xilinx提供
上传时间： 2014-11-29
上传用户：
DDR sram的官方文档,介绍了DDR sram的使用及其接口等各方面的消息资料.
上传时间： 2015-08-08
上传用户：dongbaobao
DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过
上传时间： 2015-09-18
上传用户：kytqcool
