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State Machine Coding Styles for Synthesis

  • 资源大小:123 K
  • 上传时间: 2013-10-12
  • 上传用户:borisliuyuan
  • 资源积分:2 下载积分
  • 标      签: Synthesis Machine Coding Styles

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本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点,Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.

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