本设计基于MSP430F161x/261x + CC2420/2520实验板，给出了物联网感知层的一些基本操作，包括传感器数据获取和低功耗无线数据通信两个方面。特别是对MSP430和CC2420/2520的配合给出了较为详细的说明及例程。由华东师范大学TI MSP430联合实验室提供。
上传时间： 2013-11-06
上传用户：qw12
模拟串口就是利用51的两个输入输出引脚如P1.0和P1.1,置1或0分别代表高低电平,也就是串口通信中所说的位,如起始位用低电平,则将其置0,停止位为高电平,则将其置1,各种数据位和校验位则根据情况置1或置0。至于串口通信的波特率,说到底只是每位电平持续的时间,波特率越高,持续的时间越短。如波特率为9600BPS,即每一位传送时间为1000ms/9600=0.104ms,即位与位之间的延时为为0.104毫秒。单片机的延时是通过执行若干条指令来达到目的的,因为每条指令为1-3个指令周期,可即是通过若干个指令周期来进行延时的,单片机常用11.0592M的的晶振,现在我要告诉你这个奇怪数字的来历。用此频率则每个指令周期的时间为(12/11.0592)uS,那么波特率为9600BPS每位要间融多少个指令周期呢？
上传时间： 2013-10-29
上传用户：zw380105939
特点： • 8/10 位精度 • 7 uS, 10-位单次转换时间. • 采样缓冲放大器 • 可编程采样时间 • 左/右 对齐, 有符号/无符号结果数据 • 外部触发控制 • 转换完成中断 • 模拟输入8通道复用 • 模拟/数字输入引脚复用 • 1到8转换序列长度 • 连续转换模式 • 多通道扫描方式
上传时间： 2014-12-28
上传用户：88mao
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly uSed in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.ThuS, it muSt be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally uSualand specified for TTL components (e.g. 74LS series: gates 1V/uS, clock inputs 20V/uS).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. ThuS, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10uS, it is irrelevant, which input level would be seen between thesamples. ThuS, it would be allowable for the signal to take 10uS to pass through theundefined area. Due to the sample rate of 10uS, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry muStbe uSed to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previouS sample 2) had alreadydetected a high, there is no change. If the previouS sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly uSed in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.ThuS, it muSt be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally uSualand specified for TTL components (e.g. 74LS series: gates 1V/uS, clock inputs 20V/uS).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. ThuS, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10uS, it is irrelevant, which input level would be seen between thesamples. ThuS, it would be allowable for the signal to take 10uS to pass through theundefined area. Due to the sample rate of 10uS, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
#include <reg51.h>#include<intrins.h> #define BuSY1 (DQ1==0) sbit DQ1 = P0^4; unsigned char idata TMP; unsigned char idata TMP_d; unsigned char f; void wr_ds18_1(char dat);unsigned char rd_ds18_1(); /***************延时程序，单位uS,大于10uS*************/void time_delay(unsigned char time){ time=time-10; time=time/6; while(time!=0)time--;} /*****************************************************//* reset ds18b20 *//*****************************************************/void ds_reset_1(void){ unsigned char idata count=0; DQ1=0; time_delay(240); time_delay(240); DQ1=1; return;}
上传时间： 2013-10-29
上传用户：sssnaxie
基于uSB接口的数据采集模块的设计与实现Design and Implementation of uSB-Based Data Acquisition Module路 永 伸(天津科技大学电子信息与自动化学院，天津300222)摘要文中给出基于uSB接口的数据采集模块的设计与实现。硬件设计采用以Adpc831与PDIuSBDI2为主的器件进行硬件设计，采用Windriver开发uSB驱动，并用Visual C十十6.0对主机软件中硬件接口操作部分进行动态链接库封装。关键词uSB 数据采集Adpc831 PDNSBDI2 Windriver动态链接库Abstract T hed esigna ndim plementaitono fU SB-BasedD ataA cquisiitonM oduleis g iven.Th ec hips oluitonm ainlyw ithA dpc831a ndP DTuSBD12i suSed for hardware design. The uSB drive is developed场Wmdriver, and the operation on the hardware interface is packaged into Dynamic Link Libraries场Visual C++6.0. Keywords uSB DataA cquisition Adttc831 PDfuSBD12 Windriver0 引言uS B总 线 是新一代接口总线，最初推出的目的是为了统一取代PC机的各类外设接口，迄今经历了1.0,1.1与2.0版本3个标准。在国内基于uSB总线的相关设计与开发也得到了快速的发展，很多设计者从各自的应用领域，用不同方案设计出了相应的装置[1,2]。数据采集是工业控制中一个普遍而重要的环节，因此开发基于uSB接口的数据采集模块具有很强的现实应用意义。虽然 uS B总线标准已经发展到2.0版本，但由于工业控制现场干扰信号的情况比较复杂，高速数据传输的可靠性不容易被保证，并且很多场合对数据采集的实时性要求并不高，开发2.0标准产品的成本又较1.1标准产品高，所以笔者认为，在工业控制领域，目前开发基于uSB总线1.1标准实现的数据采集模块的实用意义大于相应2.0标准模块。
上传时间： 2013-10-23
上传用户：q3290766
摘 要 瞬态仿真领域的许多工作需要获得可视化数据, 仿真电路不能将输出参数绘制成图形时研究工作将受到很大影响. 而权威电路仿真软件PSpice 在这个方面不尽如人意. 本文提出了一种有效的解决办法: 通过MATLAB 编程搭建一个PSpice 与MATLAB 的数据接口,使PSpice输出数据文件可以导入到MATLAB中绘制图形. 这令我们能够很方便地获得数据的规律以有效地分析仿真结果, 这项技术对于教学和工程实践都有比较实际的帮助.关键词: 瞬态仿真 仿真程序 PSpice MATLAB 可视化数据The Data Transfer from Pspice to MATLABWu hao Ning yuanzhong Liang yingAbstract Many works in the area of transient simulation has shown how a emulator such asPSpice can be interfaced to an control analysis package such as MATLAB to get viewdata. Thepaper describes how such interfaces can be made uSing the MATLAB programming. The platformas a typical platform will solve the problem that PSpice software sometimes can not draw the datato a picture. It can make uS find the rule from numerouS data very expediently, so we can analyzethe outcome of the simulation. And it also can be uSed in the field of education.Keywords Transient Simulation Emulator PSpice MATLAB Viewdata1 引言科学研究和工程应用常需要进行电路仿真 PSpice可进行直流 交流 瞬态等基本电路特性分析 也可进行蒙托卡诺 MC 统计分析 最坏情况 Wcase 分析 优化设计等复杂电路特性分析 它是国际上仿真电路的权威软件 而MATLAB的主要特点有 高效方便的矩阵和数组运算 编程效率高 结构化面向对象 方便的绘图功能 用户使用方便 工具箱功能强大 两者各有着重点 两种软件结合应用 对研究工作有很重要的意义香港理工大学Y. S. LEE 等人首先将PSpice和MATLAB结合 开发了电力电子电路优化用的CAD 程序MATSPICE[6] 将两者相结合的关键在于 如何用MATLAB 获取PSpice的仿真数据 对此参考文献 6 里没有详细叙述 本文着重说明用MATLAB 读取PSpice仿真数据的具体方法本论文利用MATLAB对PSpice仿真出的数据处理绘制出后者无法得到或是效果不好的仿真图形 下面就两者结合使用的例子 进行具体说明
上传时间： 2013-10-20
上传用户：wuchunzhong
uSB接口控制器参考设计,xilinx提供VHDL代码 uSb xilinx vhdl ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 2 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be uSeful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, uSA.
上传时间： 2013-10-12
上传用户：windgate
In today’s world of modular networking and telecommunications design, it is becomingincreasingly difficult to keep alignment with the many different and often changing interfaces,both inter-board and intra-board. Each manufacturer has their own spin on the way in whichdevices are connected. To satisfy the needs of our cuStomers, we muSt be able to support alltheir interface requirements. For uS to be able to make products for many cuStomers, we muStadopt a modular approach to the design. This modularity is the one issue that drives the majorproblem of shifting our bits from one modular interface to another.
上传时间： 2013-11-25
上传用户：suicone
