the-vhdl-co

A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx

A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx

标签： implementation reference provided Huffman

上传时间： 2015-07-07

上传用户：cooran
通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library.

通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library.

标签： VHDL Free-FIFO standard Project

上传时间： 2013-12-12

上传用户：天涯
the samples of VHDL very usef

the samples of VHDL very usef

标签： samples VHDL very usef

上传时间： 2015-07-25

上传用户：moerwang
Language writes with VHDL demonstrates the design on the monitor the source program用VHDL 语言写的在显示器上显示

Language writes with VHDL demonstrates the design on the monitor the source program用VHDL 语言写的在显示器上显示图案的程序

标签： the VHDL demonstrates Language

上传时间： 2015-10-14

上传用户：ardager
8051的内核(vhdl) This is version 1.1. of the MC8051 IP core. 在FPGA上运行.供有精力的人研究.

8051的内核(vhdl) This is version 1.1. of the MC8051 IP core. 在FPGA上运行.供有精力的人研究.

标签： 8051 version vhdl This

上传时间： 2013-12-16

上传用户：gdgzhym
VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register betw

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.

标签： SPI bus register effect

上传时间： 2013-12-23

上传用户：lx9076
Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of d

Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.

标签： Technology simulation simulator the

上传时间： 2013-12-26

上传用户：zl5712176
This a vhdl programme for realise an electron watch by max-plus II. The function includes time showi

This a vhdl programme for realise an electron watch by max-plus II. The function includes time showing and time setting. It may be extended to other functions like alarming clock and so forth.

标签： programme electron max-plus function

上传时间： 2013-12-26

上传用户：dbs012280
This program shows the distributions of the co-channel interference in forward and reverse link in t

This program shows the distributions of the co-channel interference in forward and reverse link in the cellular mobile system with cluster size N, when the mobile subscriber (MS) is at random positions of a cell.

标签： distributions interference co-channel the

上传时间： 2014-01-15

上传用户：z754970244
CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.

标签： specification the designed diagrams

上传时间： 2013-12-27

上传用户：yyyyyyyyyy