·Verilog HDL synThesis, A Practical Primer
标签： nbsp synThesis Practical Verilog
上传时间： 2013-04-24
上传用户：muhongqing
·Advanced ASIC Chip synThesis Using Synopsys Design Compiler,Physical Compiler and Primetime
标签： nbsp synThesis Advanced Synopsys
上传时间： 2013-04-24
上传用户：alia
直接数字频率合成（Direct Digital Fraquency synThesis,即DDFS，一般简称DDS）是从相位概念出发直接合成所需要波形的一种新的频率合成技术。
标签： Fraquency synThesis Digital Direct
上传时间： 2013-08-27
上传用户：wpt
FPGA synThesis with the Synplify Pro Tool
标签： synThesis Synplify FPGA with
上传时间： 2013-09-04
上传用户：sevenbestfei
本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for synThesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.
标签： synThesis Machine Coding Styles
上传时间： 2013-10-15
上传用户：dancnc
本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for synThesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.
标签： synThesis Machine Coding Styles
上传时间： 2013-10-12
上传用户：sardinescn
State.Machine.Coding.Styles.for.synThesis（状态机，英文,VHDL）
标签： synThesis Machine Coding Styles
上传时间： 2013-12-22
上传用户：vodssv
Simulation and synThesis Techniques for Asynchronous FIFO Design
标签： Asynchronous Simulation Techniques synThesis
上传时间： 2013-12-10
上传用户：songnanhua
FPGA synThesis with the Synplify Pro Tool
标签： synThesis Synplify FPGA with
上传时间： 2015-04-25
上传用户：guanliya
Xilinx synThesis & Simulation Design Guide
标签： Simulation synThesis Xilinx Design
上传时间： 2013-12-26
上传用户：xsnjzljj
