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spa-BUS

  • LPC315x系列ARM微控制器用户手册

    The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.

    标签: 315x LPC 315 ARM

    上传时间: 2014-01-17

    上传用户:Altman

  • Xilinx UltraScale:新一代架构满足您的新一代架构需求(EN)

      中文版详情浏览:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    标签: UltraScale Xilinx 架构

    上传时间: 2013-11-21

    上传用户:wxqman

  • AXI总线功能模块v1.1产品简介(英文资料)

    AXI Bus Functional Model v1.1 Product Brief.pdf

    标签: AXI 1.1 总线 产品简介

    上传时间: 2015-01-01

    上传用户:kbnswdifs

  • XAPP122 - Spartan-XL FPGA的Express配置

    Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui

    标签: Spartan-XL Express XAPP FPGA

    上传时间: 2015-01-02

    上传用户:nanxia

  • PLB Block RAM(BRAM)接口控制器

    The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).

    标签: Block BRAM PLB RAM

    上传时间: 2013-10-27

    上传用户:Breathe0125

  • XAPP708 -133MHz PCI-X到128MB DDR小型DIMM存储器桥

      The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.

    标签: PCI-X XAPP DIMM 708

    上传时间: 2013-11-24

    上传用户:18707733937

  • can-bus规范2.0版本

    随着串行通讯进入更多应用领域,因此,在一些应用里,需要对通讯功能的报文识别位提出分配标准化的要求。原先的地址范围由 11 个识别位定义,如果地址范围扩大,则这些应用就可以更好地由 CAN 来实现。因此引入了第二种报文格式(‘扩展格式’)的概念,其定义的地址范围更宽,由 29 位定义。

    标签: can-bus 2.0 版本

    上传时间: 2013-11-10

    上传用户:maqianfeng

  • HDMI一致性测试

      The high defi nition multimedia interface (HDMI) is fastbecoming the de facto standard for passing digitalaudio and video data in home entertainment systems.This standard includes an I2C type bus called a displaydata channel (DDC) that is used to pass extended digitalinterface data (EDID) from the sinkdevice (such as adigital TV) to the source device (such as a digital A/Vreceiver). EDID includes vital information on the digitaldata formats that the sink device can accept. The HDMIspecifi cation requires that devices have less than 50pFof input capacitance on their DDC bus lines, which canbe very diffi cult to meet. The LTC®4300A’s capacitancebuffering feature allows devices to pass the HDMI DDCinput capacitance compliance test with ease.

    标签: HDMI 测试

    上传时间: 2013-11-21

    上传用户:tian126vip

  • CAN-bus井下人员定位系统联入以太环网的解决方案V1.00

    ACNET-600/622为工业级产品,可以工作在-25℃~+75℃的温度范围内。它具有10M/100M自适应以太网接口,CAN口通信最高波特率为1Mbps,完善的支持TCP Server、TCP Client和UDP等多种工作模式,每个CAN口可支持2个TCP连接或多达2×254个UDP“连接”,通过配置软件用户可以灵活的设定相关配置参数。

    标签: CAN-bus 1.00 定位系统 方案

    上传时间: 2013-10-25

    上传用户:竺羽翎2222

  • IEEE1394Diag is a GUI application that presents a graphical view of an IEEE1394 network and provides

    IEEE1394Diag is a GUI application that presents a graphical view of an IEEE1394 network and provides the ability to perform common 1394 operations such as async reads, writes, isoc listens and talks, as well as configuration rom browsing of all nodes present on a bus.

    标签: IEEE 1394 application graphical

    上传时间: 2015-04-02

    上传用户:familiarsmile