-- DESCRIPTION : shift register -- Type : univ -- Width : 4 -- shift direction: right/left (right active high) -- -- CLK active : high -- CLR active : high -- CLR type : synchronous -- SET active : high -- SET type : synchronous -- LOAD active : high -- CE active : high -- SERIAL input : SI
标签： shift right DESCRIPTION direction
上传时间： 2013-12-02
上传用户：gxrui1991
Images with Uncertainty Efficient Algorithms for shift, Rotation, Scaling, and Registration, and Their Applications to Geosciences (2007).pdf
标签： Registration Uncertainty Algorithms Efficient
上传时间： 2016-08-23
上传用户：zhaiye
MSP-FET430P140 Demo - USART0, SPI Interface to HC165/164 shift Registers Description: Demonstrate USART0 in two-way SPI mode. Data are read from an HC165, and same data written back to the HC164. ACLK = n/a MCLK = SMCLK = default DCO = UCLK0 = DCO/2 * USART0 control bits are in different SFR s from other MSP430 s *
标签： Description Demonstrate Interface Registers
上传时间： 2013-12-28
上传用户：懒龙1988
按五次shift键,就会出现一个功能界面通过它你可以调用网页
上传时间： 2013-12-21
上传用户：ggwz258
使用89S52为核心做的USB键盘,注意修改了一下windows设备描述符以及端点处理等就行了。用了一个4*4的小键盘,有0-9十个数字键, Num Lock键,Caps Lock键,shift键,Ctrl键,Alt键,回车键等。 最多可以有三个键同时按下，如果相交的话，最多只能两个键按下
上传时间： 2013-12-14
上传用户：zhuimenghuadie
簡易MIPS CPU程式碼 此CPU包含 shift add sub and or stl beq lw sw 等功能
上传时间： 2014-01-18
上传用户：CHENKAI
双系统用户 粘滞键漏洞 shift按五下轻松破解Vista登陆密码
上传时间： 2016-10-31
上传用户：xwd2010
Top module name : shiftER (File name : shiftER.v) 2. Input pins: shift [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The shift signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2013-12-13
上传用户：himbly
Top module name : shiftER (File name : shiftER.v) 2. Input pins: shift [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The shift signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2014-01-20
上传用户：三人用菜
This m file simulates a differential phase shift keyed (DPSK) ultra wide bandwidth(UWB) system using a fifth derivative waveform equation of a Gaussian pulse.
标签： differential bandwidth simulates system
上传时间： 2014-01-03
上传用户：784533221
