sRAM-IP-CORE

This is version 1.5 of the MC8051 IP core.

This is version 1.5 of the MC8051 IP core.

标签： version This 8051 core

上传时间： 2017-04-21

上传用户：jeffery
Verilog 8051 IP Core for Cyclone II

Verilog 8051 IP Core for Cyclone II

标签： Verilog Cyclone 8051 Core

上传时间： 2017-04-28

上传用户：zaizaibang
CMON51 monitor source for debugging 8051 IP Core.

CMON51 monitor source for debugging 8051 IP Core.

标签： debugging monitor source CMON

上传时间： 2013-11-29

上传用户：zukfu
Standard 8051 IP Core

Standard 8051 IP Core

标签： Standard 8051 Core IP

上传时间： 2013-12-29

上传用户：zxc23456789
IP core of adder,8-bit width, three design concerpts with different effect.

IP core of adder,8-bit width, three design concerpts with different effect.

标签： concerpts different design effect

上传时间： 2017-05-18

上传用户：无聊来刷下
USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.

USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.

标签： speed USBHostSlave and Supports

上传时间： 2014-01-17

上传用户：sxdtlqqjl
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptiv

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

标签： configurable controller universal adaptive

上传时间： 2017-06-25

上传用户：皇族传媒
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.

This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.

标签： Tensilica OpenCores interface the

上传时间： 2013-12-21

上传用户：gonuiln
Quartus中实现的DDS 使用的是altera提供的IP core

Quartus中实现的DDS 使用的是altera提供的IP core

标签： Quartus altera core DDS

上传时间： 2017-06-27

上传用户：Breathe0125
Alera 的8051 IP core的示例文件5个

Alera 的8051 IP core的示例文件5个

标签： Alera 8051 core IP

上传时间： 2017-07-09

上传用户：cylnpy