This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上传时间： 2013-11-11
上传用户：gundamwzc
This application note describes how the existing dual-port block memories in the Spartan™-IIand Virtex™ families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in terms of bits per second will remain the same.
上传时间： 2014-01-24
上传用户：15527161163
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上传时间： 2013-11-01
上传用户：wojiaohs
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
标签： Efficient Verilog Digital Coding
上传时间： 2013-11-23
上传用户：我干你啊
Abstract: As industrial control systems (ICSs) have become increasingly connected and use more off-the-shelfcomponents, new vulnerabilities to cyber attacks have emerged. This tutorial looks at three types of ICSs:programmable logic controllers (PLCs), supervisory control and data acquisition (SCADA) systems, anddistributed control systems (DCSs), and then discusses security issues and remedies. This document alsoexplains the benefits and limitations of two cryptographic solutions (digital signatures and encryption) andelaborates on the reasons for using security ICs in an ICS to support cryptography.
上传时间： 2013-10-09
上传用户：woshinimiaoye
Have you had the exasperating experience of a laptop orPDA defi antly not responding to your commands? Youfrantically press key after key, but to no avail. As hopeturns to anger (but just before you throw the company’slaptop through the window) you slam your fi nger againstthe on/off power button. Ten seconds later, your laptopfi nally surrenders and the screen goes black in a highpitched whimper.
上传时间： 2013-12-10
上传用户：Vici
QX5305 是一款高效率，稳定可靠的高亮度LED灯驱动控制IC，内置高精度比较器，off-time控制电路，恒流驱动控制电路等，特别适合大功率，多个高亮度LED灯串恒流驱动。 QX5305采用固定off-time控制工作方式，其工作频率可高达2.5MHz，可使外部电感和滤波电容、体积减少，效率提高。 在DIM脚加PWM信号，可调节LED灯的亮度。 通过调节外置的电阻，能控制高亮度LED灯的驱动电流，使LED灯亮度达到预期恒定亮度，流过高亮度LED灯的电流可从几毫安到2安培变化。 方框图： 管脚排列图： QX5305的特性 可编程驱动电流，最高可达2A 高效率：最高达95% 宽输入电压范围：2.5V~36V 高工作频率：2.5MHz 工作频率可调：500KHz~2.5MHz 驱动LED灯功能强：LED灯串可从1个到几十个LED高亮度灯 亮度可调：通过EN端PWM，调节LED灯亮度 QX5305应用范围 干电池供电LED灯串 LED灯杯 RGB大显屏高亮度LED灯 平板显示器LED背光灯 恒流充电器控制 通用恒流源。 工作原理简述： QX5305 采用峰值电流检测和固定off-time控制方式。片内的R-S触发器分别由off-time定时器置位和CS比较器、FB比较复位，它控制外部MOSFET管并和功率电感 L、LED、肖特基二极管共同构成一个自振荡的，连续电感电流模式的升压型恒流LED驱动电路（参见图1）。 除了固定off-time控制这点外，QX5305的工作方式和普通的电流模式PWM控制型DC/DC升压电路非常相似。当工作在连续电流模式下时，流过功率电感的电流IL如图所示：
上传时间： 2013-10-26
上传用户：TF2015
两个Nokia研究人员写的W-CDMA的仿真代码。 包含信道编码，交织，速率匹配，调制，扩频，信道模型，RACK接收机和相应的解码程序
上传时间： 2013-12-25
上传用户：huannan88
TIMER.ASM ********* [ milindhp@tifrvax.tifr.res.in ] Set Processor configuration word as = 0000 0000 1010 b. a] -MCLR tied to VDD (internally). b] Code protection off. c] WDT disabled. d] Internal RC oscillator [4 MHZ].
标签： configuration Processor milindhp tifrvax
上传时间： 2015-05-24
上传用户：wqxstar
The Hopfield model is a distributed model of an associative memory. Neurons are pixels and can take the values of -1 (off) or +1 (on). The network has stored a certain number of pixel patterns. During a retrieval phase, the network is started with some initial configuration and the network dynamics evolves towards the stored pattern which is closest to the initial configuration.
标签： model distributed associative Hopfield
上传时间： 2015-06-17
上传用户：l254587896
