中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
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上传一分自己用得顺心的AD10集成库
上传时间： 2013-12-11
上传用户：hullow
QuartusII中利用免费IP核的设计 作者：雷达室 以设计双端口RAM为例说明。 Step1：打开QuartusII，选择File—New Project Wizard，创建新工程，出现图示对话框，点击Next；
上传时间： 2013-10-18
上传用户：909000580
使用Nios II软件构建工具 This chapter describes the Nios® II Software Build Tools (SBT), a set of utilities and scripts that creates and builds embedded C/C++ application projects, user library projects, and board support packages (BSPs). The Nios II SBT supports a repeatable, scriptable, and archivable process for creating your software product. You can invoke the Nios II SBT through either of the following user interfaces: ■ The Eclipse™ GUI ■ The Nios II Command Shell The purpose of this chapter is to make you familiar with the internal functionality of the Nios II SBT, independent of the user interface employed.
上传时间： 2013-10-12
上传用户：china97wan
面向Eclips的Nios II软件构建工具手册 The Nios® II Software Build Tools (SBT) for Eclipse™ is a set of plugins based on the Eclipse™ framework and the Eclipse C/C++ development toolkit (CDT) plugins. The Nios II SBT for Eclipse provides a consistent development platform that works for all Nios II embedded processor systems. You can accomplish all Nios II software development tasks within Eclipse, including creating, editing, building, running, debugging, and profiling programs.
上传时间： 2013-11-02
上传用户：瓦力瓦力hong
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2014-11-26
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This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
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讨论、研究高性能覆铜板对它所用的环氧树脂的性能要求，应是立足整个产业链的角度去观察、分析。特别应从HDI多层板发展对高性能CCL有哪些主要性能需求上着手研究。HDI多层板有哪些发展特点，它的发展趋势如何——这都是我们所要研究的高性能CCL发展趋势和重点的基本依据。而HDI多层板的技术发展，又是由它的应用市场——终端电子产品的发展所驱动（见图1）。 图1 在HDI多层板产业链中各类产品对下游产品的性能需求关系图 1．HDI多层板发展特点对高性能覆铜板技术进步的影响1.1 HDI多层板的问世，对传统PCB技术及其基板材料技术是一个严峻挑战20世纪90年代初，出现新一代高密度互连（High Density Interconnection，简称为 HDI）印制电路板——积层法多层板（Build—Up Multiplayer printed board，简称为 BUM）的最早开发成果。它的问世是全世界几十年的印制电路板技术发展历程中的重大事件。积层法多层板即HDI多层板，至今仍是发展HDI的PCB的最好、最普遍的产品形式。在HDI多层板之上，将最新PCB尖端技术体现得淋漓尽致。HDI多层板产品结构具有三大突出的特征：“微孔、细线、薄层化”。其中“微孔”是它的结构特点中核心与灵魂。因此，现又将这类HDI多层板称作为“微孔板”。HDI多层板已经历了十几年的发展历程，但它在技术上仍充满着朝气蓬勃的活力，在市场上仍有着前程广阔的空间。
上传时间： 2013-11-19
上传用户：zczc
工作环境设置及软件安装这章介绍工作环境的设置及软件安装方面知识。为什么要进行工作环境设置呢？因为现在的PCB 工程师要设计的文件很多。文件多了如果不进行管理就会很混乱，导致以后的维护十分困难。所以要从刚开始学习的时候养成一个好的操作习惯，这是很有必要的。2.1 建立自己的工作目录在电脑的桌面上打开我的电脑，在我的电脑中打开D盘。在D 盘中建立三个文件夹。分别为“D：\EDA”“D：\EDA_LIB”“D：\EDA_PROJECT 三个文件夹”。如下图所示：图2-1-1 “建立工作目录”建立好三个文件夹后，在这三个文件夹中分别另建立一个新文夹，并命名为Protel99se。三个文件夹的作用分别是：EDA文件夹是用来存放安装文件；EDA—LIB 文件夹是用来存放元件库。EDA—PROJECT 文件夹是用来存放设计数据。2.2 对Protel 99se 进行安装设置好工作目录后，就可以对软件进行安装。图2-1-2就是Protel 99se的安装程序。其中“Protel99SP6”是升级补丁，“Protel99 汉化”是汉化文件。（1）双击Setup 安装图标对软件进行安装。
上传时间： 2013-10-31
上传用户：jrsoft
ADAM-5510KW中FPID/PID功能块之实现及应用一、 ADAM-5510KW实现PID控制的方法1、ADAM-5510KW可以使用Multiprog软件提供的FPID和PID功能块来实现PID控制。2、ADAM-5510KW对可以使用的PID控制回路并无限制，实际上，取决于Scan Rate，ScanRate越低，则允许的PID回路越多。3、在实际应用中，流量、液位、压力、温度等等对象都可以进行控制。对于流量、液位、压力等等参数可以用传感器或变送器转换为电压/电流信号接入模拟量输入模块ADAM-5017进行采集；对于温度可以用热电偶模块ADAM-5018或热电阻模块ADAM-5013进行采集；输出的执行机构例如调节阀、风扇等等可由模拟量输出模块ADAM-5024进行控制。二、 ADAM-5510KW中如何调用FPID/PID功能块1、FPID功能块在ProconOS.fwl库中，先将库添加进Project中。
上传时间： 2013-10-12
上传用户：it男一枚
