在使用DBCA之前，先检视一下目前环境。以我的系统为例：作业系统为SUSE LINUX 7.2，安装了oracle 9i Enterprise Edition Release 9.0.1,Oracle 9i资料库的oraclde SID设定为ora901.
上传时间： 2013-10-29
上传用户：BOBOniu
两节锂电充电IC-ASC8512 ASC8512 为开关型两节锂聚合物电池充电管理芯片，非常适合于便携式设备的充电管理应用。ASC8512 集内置功率MOSFET、高精度电压和电流调节器、预充、充电状态指示和充电截止等功能于一体，采用TSSOP-14、SSOP-14两种封装形式。ASC8512对电池充电分为三个阶段：预充（Pre-charge）、恒流（CC／Constant Current）、恒压（CV／Constant Voltage）过程，恒流充电电流通过外部电阻决定，最大充电电流为2A.ASC8512 集成电流限制、短路保护，确保充电芯片安全工作。ASC8512 集成NTC 热敏电阻接口，可以采集、处理电池的温度信息，保证充电电池的安全工作温度。 两节锂电池充电IC ASC8512特点： 1.充2节锂离子和锂聚合物电池 2.开关频率达400K 3.充电电流最大可做2A 4.输入电压9V到18V 5.电池状态检测 6.恒压充电电压值可通过外接电阻微调 7.千分之五的充电电压控制精度 5.防反向保护电路可防止电池电流倒灌 6.NTC 热敏接口监测电池温度 7.LED充电状态指示 8.工作环境温度范围：-20℃～70℃ 9.TSSOP-14 应用领域：应用 ●手持设备，包括医疗手持设备 ●Portable-DVD，PDA，移动蜂窝电话及智能手机 ●上网本、平板电脑、MID ●自充电电池组
上传时间： 2013-11-06
上传用户：chfanjiang
Demonstration circuit 1562A is an engineering toolto design and evaluate the LTC699X-X family ofTimerBlox circuits. The center section of the boardcontains a pre-configured TimerBlox function.DC1562A comes in twelve timing function variationsas outlined in Table 1.Surrounding the center board is a ”playground”prototyping area. The prototyping area has padsfor Dip-8, S8, MS8, or S6 packages with breadboarding connections to each pin and two convenientpower buses and ground bus surrounding theentire area. This area is for conditioning signals tocontrol the timer function and for adding loads controlled in time.
上传时间： 2013-10-18
上传用户：如果你也听说
STM32，5110液晶显示声纳探鱼器200KHz，带电路图，精确到厘米 MC34063升压，大声压发射，实际板子上滤波电路没要（电路图上的滤波电阻电容电感没焊，开路或者短路）。一般200KHz的换能器在水里面的耦合比较好，在空气中发射出来的（或者接收的）强度很低。 用的MOSFET Relay，contact和release时间都可以做到很小，不过选的是比较低端器件，所以最近测量距离为70cm。 开源啦开源啦 架构为状态机+任务流，Task都是放在函数指针数组里面的 Task分两种，routine的和错误处理的 5110液晶的SPI用的DMA 基本上STM32和C语言高阶的特征都用上了，稍微修改直接可以商用 Open Issue 偶尔会hardware fault或者memory fault，然后watchdog重启， 应该比较好解决，仔细检查下就好 有什么问题代码的file comment里面有我联系地址 有能搞到好的器件也请知会我，多谢了 接下来准备把它装到船模上，用以前四轴的那套东西，就看什么时候有时间了
上传时间： 2013-10-28
上传用户：songyue1991
BIT_SELFREFRESH EQU (1<<22) ;定义SDRAM自刷新标志位 16 17 ;Pre-defined constants 预定义6种工作模式 18 USERMODE EQU 0x10 ;用户模式 19 FIQMODE EQU 0x11 ;快速中断模式 20 IRQMODE EQU 0x12 ;中断模式 21 SVCMODE EQU 0x13 ;监管模式 22 ABORTMODE EQU 0x17 ;异常中断模式 23 UNDEFMODE EQU 0x1b ;未定义模式 24 25 MODEMASK EQU 0x1f ;模式掩码 26 NOINT EQU 0xc0 ;取消中断 27 28 ;The location of stacks;设置6种工作模式的堆栈的起始地址 29 ;在option.inc中定义了_STACK_BASEADDRESS EQU 0x33ff8000 30 UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~ 31 SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~ 32 UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~ 33 AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~ 34 IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~ 35 FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~
上传时间： 2013-10-07
上传用户：m62383408
AVR Studio 4.12 includes new device support and numerous overall enhancements;new breakpoint system, integrated AVR GCC development and improved docking system!See release notes for more details.
上传时间： 2013-12-29
上传用户：450976175
FeaturesThe following standard features are provided.• Choice of RTOS scheduling policy1. Pre-emptive:Always runs the highest available task. Tasks of identical priorityshare CPU time (fully pre-emptive with round robin time slicing).2. Cooperative:Context switches only occur if a task blocks, or explicitly callstaskYIELD().• Co-routines (light weight tasks that utilise very little RAM).• Message queues• Semaphores [via macros]• Trace visualisation ability (requires more RAM)• Majority of source code common to all supported development tools• Wide range of ports and examples
上传时间： 2013-10-13
上传用户：13162218709
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
上传时间： 2014-01-13
上传用户：竺羽翎2222
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
标签： CPLD
上传时间： 2013-10-22
上传用户：李哈哈哈
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
标签： Transceiver Virtex Wizar GTP
上传时间： 2013-10-23
上传用户：leyesome
