Analysis of blind data hiding using discrete cosine transform phase modulation。
标签： modulation transform Analysis discrete
上传时间： 2013-12-27
上传用户：yzy6007
编译原理大作业---tiger编译器 包括semant,translate,mipsframe,regalloc等所有phase 懂的人自会知道
标签： mipsframe translate regalloc semant
上传时间： 2016-11-01
上传用户：lanwei
GPS Data processing: Code and Phase
标签： processing Phase Data Code
上传时间： 2013-12-12
上传用户：sunjet
This m file simulates a differential phase shift keyed (DPSK) ultra wide bandwidth(UWB) system using a fifth derivative waveform equation of a Gaussian pulse.
标签： differential bandwidth simulates system
上传时间： 2014-01-03
上传用户：784533221
script for generting transmit waveforms in a minimum shift keying, a form of continuous phase frequency shift keying
标签： continuous generting waveforms transmit
上传时间： 2016-11-30
上传用户：ANRAN
A high-speed variable phase accumulator for an ADPLL architecture
标签： architecture accumulator high-speed variable
上传时间： 2013-11-26
上传用户：wpt
A Top-Down Verilog-A Design on the digital phase-lockedmloop
标签： phase-lockedmloop Verilog-A Top-Down digital
上传时间： 2013-12-02
上传用户：silenthink
Ethernet Services Attributes Phase
标签： Attributes Ethernet Services Phase
上传时间： 2013-12-13
上传用户：xhz1993
A Matlab code to plot the matched filter for 16-element linear array with constant phase weights on transmit and receive LFM waveform parameters.计算具有收发线性调频波形参数的相位权重的16单元线性匹配滤波器
标签： constant matched element weights
上传时间： 2014-07-19
上传用户：siguazgb
DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上传时间： 2014-11-01
上传用户：l254587896
