Q01、如何使一条走线至两个不同位置零件的距离相同? 您可先在Design/Rule/High Speed/Matched Net Lengths的规则中来新增规则设定,最 后再用Tools/EqualizeNet Lengths 来等长化即可。 Q02、在SCHLIB中造一零件其PIN的属性，如何决定是Passive, Input, I/O, Hi- Z,Power,…..？在HELP中能找到说明吗？市面有关 SIM？PLD？的书吗？或贵公司有讲义？ 你可在零件库自制零件时点选零件Pin脚,并在Electrical Type里,可以自行设定PIN的 属性,您可参考台科大的Protel sch 99se 里 面有介绍关于SIM的内容。 Q03、请问各位业界前辈,如何能顺利读取pcad8.6版的线路图,烦请告知 Protel 99SE只能读取P-CAD 2000的ASCII档案格式,所以你必须先将P-CAD8.6版的格式 转为P-CAD 2000的档案格式,才能让Protel读取。
标签： Protel
上传时间： 2013-11-22
上传用户：daxigua
《Protel99SE电路设计与仿真》 第1章 概述第2章 设计与绘制电路原理图第3章 Sch元件图形的绘制第4章 电路原理图的常用处理技术第5章 设计印制电路板图PCB第6章 PCB的自动化设计第7章 Protel 99 SE电路设计仿真第8章 PCB信号完整性分析第9章 实验指导附录一 Protel 99 SE电路设计仿真实例
上传时间： 2013-11-19
上传用户：253189838
手机PCB之PROTEL设计图纸
上传时间： 2013-11-23
上传用户：boyaboy
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
标签： Efficient Verilog Digital Coding
上传时间： 2013-11-22
上传用户：han_zh
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上传时间： 2014-12-23
上传用户：xinhaoshan2016
本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.
标签： Synthesis Machine Coding Styles
上传时间： 2013-10-15
上传用户：dancnc
本文详细讨论了VHDL语句对PLD设计的影响和设计经验，经典文章，值得仔细阅读消化。,PLD Programming Using VHDL
标签： Programming Using VHDL PLD
上传时间： 2013-11-17
上传用户：teddysha
本章的主要内容介绍Allegro 如何载入Netlist，进而认识新式转法和旧式转法有何不同及优缺点的分析，通过本章学习可以对Allegro 和Capture 之间的互动关係，同时也能体验出Allegro 和Capture 同步变更属性等强大功能。
上传时间： 2013-12-23
上传用户：ANRAN
本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
标签： Verilog verilog System VHDL
上传时间： 2013-10-16
上传用户：牛布牛
本文讨论了如何设计有效的testbench，适合刚接触testbench不久的用户阅读提高 （xilinx公司编写）
标签： Testbenches Efficient Writing
上传时间： 2013-10-18
上传用户：xiaodu1124
