ORCAD在使用的时候总会出现这样或那样的问题…但下这个问题比较奇怪…在ORCAD中无法输出网表…弹出下面的错误….这种问题很是奇怪…Netlist Format: tango.dllDesign Name: D:\EDA_PROJECT\PROTEL99SE\YK\SV3200\MAIN.DSNERROR [NET0021] Cannot get pARt.[FMT0024] Ref-des not found. Possible Logical/Physical annotation conflict.[FMT0018] Errors processing intermediate file找了一天没找到问题…终于在花了N多时间后发现问题所在…其实这个问题就是不要使用ORCAD PSPICE 库里面的元件来画电路图…实际中我是用了PSPICE里面和自己制作的二种电阻和电容混合在一起…就会出现这种问题…
上传时间： 2013-11-21
上传用户：zaocan888
superpro 3000u 驱动 PIC16C65B@QFP44 [SA245] PIC16C65B: pARt number QFP44: Package in QFP44 SA245: Adapter purchase number AM29DL320GT@FBGA48 [SA642+B026] AM29DL320GT: pARt number FBGA48: Package in FBGA48 SA642: Adapter purchase number (Top board with socket) B026: Adapter purchase number (Bottom board, exchangable for different pARts) 87C196CA@PLCC68(universal adapter) [PEP+S414T] 87C196CA: pARt number PLCC68: Package in PLCC68 universal adapter: this adapter is valid for all pARts in this package PEP: The PEP (Pin-driver Expansion Pack necessary to work with the adapter S414T) S414T: Adapter purchase number (Universal for all pARts in this package) S71PL127J80B@FBGA64(special adapter) [(SA642A-B079A-Y096AF001)] S71PL127J80B: pARt number FBGA64: Package in FBGA64 special adapter: this adapter is valid for this
上传时间： 2013-10-23
上传用户：Avoid98
网上疯传的Excel BOM经典脚本，相信诸位PADS用户再熟悉不过了吧！ 但是它还有缺点： 1.元件封装不能转换。(元件位号为R/C/L的0402/063/0805/1206封装自动转换统一的对应封装，以方便统计。) 2.元件参数转换。(电阻的转换0R时由0mR修正为0R,KR/MR修正为K/M。) 3.不能按元件的SMD属性来分类统计。 4.有些公司在制作PADS库元件时，已经为元件建立了pARt ID。导出BOM时需要元件的pARt ID属性。 5.不能导出元件坐标。（本人改进导出元件几何中心坐标，以便贴片生产之用。） 6.不能导出跳线。 7.不能支持WPS。 8.不能自定义导出元件的pARt ID属性。 9.不能自定义位号之间连接符号。 10.导出BOM特殊字符乱码，比如常见的±/µ/Ω等。（PADS9.5在中文状态下导出BOM就不会乱码， 暂时还没有更好的解决办法，不过可以在Excel中替换解决。） 11.加载与运行脚本步骤繁冗；运行速度比较慢。（本人改进的代码速度绝对不会比之前的慢。）
上传时间： 2015-01-01
上传用户：rolypoly152
通过以太网远程配置Nios II 处理器 应用笔记 Firmware in embedded hardware systems is frequently updated over the Ethernet. For embedded systems that comprise a discrete microprocessor and the devices it controls, the firmware is the software image run by the microprocessor. When the embedded system includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If the FPGA includes a Nios® II soft processor, you can upgrade both the Nios II processor—as pARt of the FPGA image—and the software that the Nios II processor runs, in a single remote configuration session.
上传时间： 2013-11-22
上传用户：chaisz
Nios II定制指令用户指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,pARt of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上传时间： 2013-10-12
上传用户：kang1923
This application note provides a detailed description of the SpARtan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the pARt. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor pARtial reconfiguration or pARtial readback.
上传时间： 2013-11-16
上传用户：qingdou
This application note shows how to achieve low-cost, efficient serial configuration for SpARtan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, pARt count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing SpARtan configuration.In pARticular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a SpARtan design in the field by sending thebitstream over a network.
上传时间： 2013-11-01
上传用户：wojiaohs
The standard that governs the design of avioniccomponents and systems, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard aresketchy. And once an entity develops a process thatachieves compliance, the details of how compliancewas achieved become pARt of the intellectualproperty of that entity. This white paper focuses onthe details of developing a DO-254 compliantprocess for the design of FPGAs.
上传时间： 2013-11-03
上传用户：ysystc670
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the pARt is externally programmed?
上传时间： 2013-10-20
上传用户：磊子226
Field Programmable Gate Arrays (FPGAs) are becoming a critical pARt of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.
上传时间： 2013-10-22
上传用户：lmq0059
