针对目前汽车追尾事件频发问题，提出一种防汽车车前和车后追尾的安全装置设计。该设计以高性能、低功耗的8位AVR微处理器ATmega8L为核心，结合霍尔式车速传感器、激光雷达测距装置和MMA7260QT加速度传感器，能够兼顾车前和车后，摒弃以往设计中只考虑车前或车后单一性缺点，尤其适用于高速、夜晚或新手行车。 Abstract: Aiming at the high frequency of vehicle rear-end collision，a safe device design of anti-vehicle rear-end collision is presented.In the design，the high-performance，low-power8-bit AVR microProcessor ATmega8L is utilized as a core combined with Hall-type speed sensor，laser-radar ranging devices and the acceleration sensor MMA7260QT.The design considers both the front and back of a car，and overcomes the drawbacks of former designs in which only the front or the back of the car is considered，so it is especially suitable for high-speed，night or the beginner’s driving.
上传时间： 2013-10-14
上传用户：GavinNeko
实时时钟是微机保护装置的重要部件，在讨论PCF8583结构与功能的基础上，提出采用dsPIC33F系列微处理器与串行I2C时钟PCF8583的接口设计方案，给出了相应的接口电路与软件流程。该设计方案结构简单，可靠性高，开发周期短，具有一定的实用与参考价值。所设计的微机保护装置已投入现场运行，效果良好。 Abstract: Real-time clock chip is an important part in microcomputer protection device.Based on discussing the structure and function of PCF8583，a new interface scheme which uses dsPIC33F microProcessor and serial clock chip（I2C）PCF8583is proposed.The method of the circuit design and the main software flow are introduced in this paper.The scheme has simple structure，higher reliability and shorter exploitation cycle，so has definite practicality or reference value.The microcomputer protection device has been put into operation with better effects.
上传时间： 2013-11-18
上传用户：Thuan
数字信号处理器dsPIC33F集多通道高精度A/D转换、多通讯模式、看门狗、CMOS Flash技术等于一体，其内部可完成所有数据操作，实现总线不出芯片技术。将该处理器应用于微机保护装置，提出基于dsPIC33F微处理器的微机保护装置的设计方案，给出相应的接口电路与软件流程。该设计方案结构简单，性价比及可靠性高，开发周期短，具有一定的实用推广价值。所研制的微机保护装置现场运行效果良好。 Abstract: The dsPIC33F microProcessor has a plentiful interior resource which contains multi-channel，high precision A/D converters，multi-communication module，watchdog，CMOS Flash technology，and so on.All data manipulations is accomplished interiorly.What is more，it makes the technology that bus does not go beyond the chip comes into practice.The paper put forwards a design scheme based on dsPIC33F microProcessor.The scheme has the advantages of simple structure，high reliability and shortened exploitation cycle.What is more，it has definite practicality and reference.The microcomputer protection device has been put into operation with excellent effects.
上传时间： 2013-11-16
上传用户：开怀常笑
主要介绍了以PIC18F2480单片机为处理器，基于可编程多路开关检测接口器件MC33993实现的车用多路开关检测接口电路的设计。该设计克服了以往基于分立元件的检测接口电路的弊端，简化了接口电路设计，保证了车用开关工作的可靠性和安全性。 Abstract: The design of automotive multiple switch detection interface circuit based on MC33993 is introduced mainly which adopts PIC18F2480 single chip microProcessor.This circuit overcomes shortage of traditional design which contains many schism elements, and the application of MC33993 also predigests the whole design of interface circuit and guarantees the dependability and security of the switch.
上传时间： 2013-11-19
上传用户：star_in_rain
Bootloader是微处理器上电时运行的第一段代码，它可以通过通信接口实现对微处理器内部应用程序的更新升级，为网络化嵌入式产品的应用程序升级带来极大的便利。由于目前没有统一嵌入式系统的Bootloader。基于NEC 78K0系列单片机自编程原理，设计出一个适用于78K0/Fx2系列单片机的Bootloader，并能够通过单片机串口在线升级应用程序。 Abstract: Bootloader is the first piece of code executed after microProcessor startup. It makes the embedded product’s firmware update conveniently through communication interface. However， no unified bootloader is available for all kinds of microProcessor products. Based on the principle of self-programming NEC 78K0s’ series， a useful Bootloader which is suitable for 78K0/Fx2s’ series MCU is designed，the design can update the application through serial ports.
标签： Bootloader MCU 自编程
上传时间： 2013-10-26
上传用户：fang2010
汇编器在微处理器的验证和应用中举足轻重，如何设计通用的汇编器一直是研究的热点之一。本文提出了一种开放式的汇编器系统设计思想，在汇编语言与机器语言间插入中间代码CMDL（code mapping description language）语言，打破汇编语言与机器语言的直接映射关系，由此建立起一套描述汇编语言与机器语言的开放式映射体系。基于此开放式映射体系开发了一套汇编器系统，具有较高层次上的通用性和可移植性。【关键词】指令集，CMDL，汇编器，开放式 Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microProcessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【关键词】instruction set, symbol table, assembler, lexical analysis, retargetability
上传时间： 2013-10-10
上传用户：meiguiweishi
本文依据集成电路设计方法学，探讨了一种基于标准Intel 8086 微处理器的单芯片计算机平台的架构。研究了其与SDRAM，8255 并行接口等外围IP 的集成，并在对AMBA协议和8086 CPU分析的基础上，采用遵从AMBA传输协议的系统总线代替传统的8086 CPU三总线结构，搭建了基于8086 IP 软核的单芯片计算机系统，并实现了FPGA 功能演示。关键词：微处理器； SoC；单芯片计算机；AMBA 协议 Design of 8086 CPU Based Computer-on-a-chip System（School of Electrical Engineering and Automation, Heifei University of Technology, Hefei, 230009,China）Abstract: According to the IC design methodology, this paper discusses the design of one kind of Computer-on-a-chip system architecture, which is based on the standard Intel8086 microProcessor,investigates how to integrate the 8086 CPU and peripheral IP such as, SDRAM controller, 8255 PPI etc. Based on the analysis of the standard Intel8086 microProcessor and AMBA Specification,the Computer-on-a-chip system based on 8086 CPU which uses AMBA bus instead of traditional three-bus structure of 8086 CPU is constructed, and the FPGA hardware emulation is fulfilled.Key words: microProcessor; SoC; Computer-on-a-chip; AMBA Specification
上传时间： 2013-12-27
上传用户：kernor
In this document, the term Ô60xÕ is used to denote a 32-bit microProcessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microProcessors. Note that this does not include the PowerPC 602ª microProcessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
上传时间： 2013-10-08
上传用户：18711024007
The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroProcessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microProcessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29
上传时间： 2013-11-04
上传用户：as275944189
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microProcessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microProcessor.
上传时间： 2013-10-15
上传用户：euroford
